# US 10,312,377 B2 · Localized fin width scaling using a hydrogen anneal

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- Number: US 10,312,377 B2
- Document ID: US10312377B2
- Status: Granted
- Kind: B2
- Application number: 15/291,137
- Filed: 2016-10-12
- Published: 2017-02-02
- Granted: 2019-06-04
- Earliest claimed: 2013-06-04
- Assignees: International Business Machines Corporation; Renesas Electronics Corporation
- Applicants: International Business Machines Corporation; Renesas Electronics Corporation
- Inventors: Veeraraghavan S. Basker; Shogo Mochizuki; Tenko Yamashita; Chun-Chen Yeh
- Web page: https://patentgrep.com/patent/US10312377B2

## CPC

- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6213: {having rounded corners}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/642: {Chemical etching}
- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.

## Claims

### Claim 1

A transistor, comprising:
at least one semiconductor fin formed on a substrate, wherein a profile of the at least one semiconductor fin is entirely convex and is widest at the bottom and tapers toward the top, and wherein the at least one semiconductor fin is thinner in a channel region than in source and drain regions and has rounded corners; and
a gate stack on the channel region of the at least one semiconductor fin.

### Claim 2 (depends on 1)

The transistor of claim 1, further comprising a spacer over the at least one semiconductor fin, separating the channel region from a respective source or drain region.

### Claim 3 (depends on 2)

The transistor of claim 2, wherein the spacer contacts the substrate without undercut.

### Claim 4 (depends on 2)

The transistor of claim 2, further comprising a shielding spacer layer that thickens the spacer to protect the source and drain regions of the at least one semiconductor fin from etching.

### Claim 5 (depends on 1)

The transistor of claim 1, wherein a plurality of semiconductor fins are merged in the source and drain regions with epitaxially grown additional fin material that connects original material of the plurality of semiconductor fins.

### Claim 6 (depends on 1)

The transistor of claim 1, wherein the at least one semiconductor fin is hydrogen-annealed at about 800 degrees Celsius and at a pressure of about 10 Torr.

### Claim 7 (depends on 1)

The transistor of claim 1, wherein there is an undercut gap between the at least one semiconductor fin and the substrate and wherein the at least one semiconductor fin is rounded to form nanowires.

### Claim 8 (depends on 1)

The transistor of claim 1, further comprising an oxide capping layer on the at least one semiconductor fin.

### Claim 9

A transistor, comprising:
at least one semiconductor fin formed on a substrate, wherein a profile of the at least one semiconductor fin is entirely convex and is widest at the bottom and tapers toward the top, and wherein the at least one semiconductor fin is thinner in a channel region than in source and drain regions and has rounded corners;
a gate dielectric layer on the channel region of the at least one semiconductor fin; and
a gate structure on the gate dielectric layer.

### Claim 10 (depends on 9)

The transistor of claim 9, further comprising a spacer over the at least one semiconductor fin separating the channel region from a respective source or drain region.

### Claim 11 (depends on 10)

The transistor of claim 10, wherein the spacer contacts the substrate without undercut.

### Claim 12 (depends on 10)

The transistor of claim 10, further comprising a shielding spacer layer that thickens the spacer to protect the source and drain regions of the at least one semiconductor fin from etching.

### Claim 13 (depends on 9)

The transistor of claim 9, wherein a plurality of semiconductor fins are merged in the source and drain regions with epitaxially grown additional fin material that connects original material of the plurality of semiconductor fins.

### Claim 14 (depends on 9)

The transistor of claim 9, wherein the at least one semiconductor fin is hydrogen-annealed at about 800 degrees Celsius and at a pressure of about 10 Torr.

### Claim 15 (depends on 9)

The transistor of claim 9, wherein there is an undercut gap between the at least one semiconductor fin and the substrate and wherein the at least one semiconductor fin is rounded to form nanowires.

### Claim 16 (depends on 9)

The transistor of claim 9, further comprising an oxide capping layer on the at least one semiconductor fin.

### Claim 17

A transistor, comprising:
at least one semiconductor fin formed on a substrate, wherein the at least one semiconductor fin is thinner in a channel region than in source and drain regions and have rounded corners;
an oxide capping layer on the at least one semiconductor fin;
a gate dielectric layer on the channel region of the at least one semiconductor fin; and
a gate structure on the gate dielectric layer.