# US 10,312,376 B2 · Thin film transistor and method for manufacturing the same

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- Number: US 10,312,376 B2
- Document ID: US10312376B2
- Status: Granted
- Kind: B2
- Application number: 15/128,202
- Filed: 2016-08-11
- Published: 2018-08-02
- Granted: 2019-06-04
- Earliest claimed: 2016-07-20
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Yang Liu
- Web page: https://patentgrep.com/patent/US10312376B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 84/01: Manufacture or treatment
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/0312: {characterised by the gate electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present provides a thin film transistor, which comprises: a gate on the substrate; a gate insulating layer; the embossed portion defining a first end in which a first active layer is formed, and a second end in which a second active layer is formed; a first source connected to the first active layer and a second source connected to the second active layer; a passivation layer; a first through hole and a second through hole defined in the passivation layer; and a drain formed on the passivation layer and extending through the first and second through hole to interconnect the first and second active layers, respectively. By this arrangement, a first distance defined between the drain with respect to a first contact surface of the first source layer located on the flattened portion of the embossed portion will equal to the height of the embossed portion. In addition, a second distance defined between the drain with respect to a second contact surface of the second source layer located on the flattened portion of the embossed portion will equal to the height of the embossed portion as well. By implementation of the technology provided by the present invention, a thin film transistor of shortened channel can be realized such that the thin film transistor is benefited with a larger aspect ratio so as to entertain a larger on-state current.

## Claims

### Claim 1

A thin film transistor, comprising:
a substrate;
a gate on the substrate;
a gate insulating layer covering the substrate and the gate creating an embossed portion in which the gate is located, and a flattened portion which contains only substrate;
the embossed portion defining a first end in which a first active layer is formed, and a second end in which a second active layer is formed, wherein both the first and second active layers extends along a sidewall of the embossed portion to the flattened portion;
a first source connected to the first active layer and a second source connected to the second active layer, which are interconnected to each other;
a passivation layer covering the first active layer, the second active layer, the first source, the second source and gate insulating layer;
a first through hole defined in the passivation layer exposing the first active layer, and a second through hole defined in the passivation layer exposing the second active layer; and
a drain formed on the passivation layer and extending through the first and second through hole to interconnect the first and second active layers, respectively; a first distance defined between a contact surface between the drain a portion of the first active layer located on the embossed portion and a contact surface between the first source and a portion of the first active layer located on the fattened portion is equal to the height of the embossed portion, and a second distance defined between a contact surface between the drain and a portion of the second active layer located on the embossed portion and a contact surface between the second source and a portion of the second active layer located on the fattened portion is equal to the height of the embossed portion as well.

### Claim 2 (depends on 1)

The thin film transistor as recited in claim 1, wherein the first source is located on the first active layer extending to the flattened portion, and the second source is located on the second active layer extending to the flattened portion; and wherein the first and second through holes expose the first and second active layers located on the embossed portion.

### Claim 3 (depends on 2)

The thin film transistor as recited in claim 2, wherein cross section of both the gate and the embossed portion are shapes of trapezoid and the sidewall of the embossed portion is oblique.

### Claim 4 (depends on 2)

The thin film transistor as recited in claim 2, the middle of the gate is embossed, and cross section of both which and the embossed portion are shapes of trapezoid and the sidewall of the embossed portion is oblique.

### Claim 5 (depends on 1)

The thin film transistor as recited in claim 1, wherein the first source is located on the first active layer on the embossed portion, and the second source is located on the second active layer on the embossed portion; and wherein the first and second through holes expose the first and second active layers located on the flattened portion.

### Claim 6 (depends on 5)

The thin film transistor as recited in claim 5, wherein cross section of both the gate and the embossed portion are shapes of trapezoid and the sidewall of the embossed portion is oblique.

### Claim 7 (depends on 5)

The thin film transistor as recited in claim 5, the middle of the gate is embossed, and cross section of both which and the embossed portion are shapes of trapezoids and the sidewall of the embossed portion is oblique.

### Claim 8 (depends on 1)

The thin film transistor as recited in claim 1, wherein the first source is located between the flattened portion and the first active layer extending to the flattened portion, and the second source is located between the flattened portion and the second active layer extending to the flattened portion; and wherein the first and second through holes expose the first and second active layers located on the embossed portion.

### Claim 9 (depends on 8)

The thin film transistor as recited in claim 8, wherein cross section of both the gate and the embossed portion are shapes of trapezoid, and the sidewall of the embossed portion is oblique.

### Claim 10 (depends on 8)

The thin film transistor as recited in claim 8, the middle of the gate is embossed, and cross section of both which and the embossed portion are shapes of trapezoid and the sidewall of the embossed portion is oblique.

### Claim 11 (depends on 1)

The thin film transistor as recited in claim 1, wherein cross section of both the gate and the embossed portion are shapes of trapezoid and the sidewall of the embossed portion is oblique.

### Claim 12 (depends on 1)

The thin film transistor as recited in claim 1, the middle of the gate is embossed, and cross section of both which and the embossed portion are shapes of trapezoid and the sidewall of the embossed portion is oblique.

### Claim 13

A method of manufacturing a thin film transistor, comprising:
forming a gate on a substrate;
forming a gate insulating layer covering the substrate and the gate creating an embossed portion in which the gate is located, and a flattened portion which contains only substrate;
forming the embossed portion defining a first end in which a first active layer is formed, and a second end in which a second active layer is formed, wherein both the first and second active layers extends along a sidewall of the embossed portion to the flattened portion;
forming a first source connected to the first active layer and forming a second source connected to the second active layer, which are interconnected to each other;
forming a passivation layer covering the first active layer, the second active layer, the first source, the second source and gate insulating layer;
forming a first through hole defined in the passivation layer exposing the first active layer, and a second through hole defined in the passivation layer exposing the second active layer; and
forming a drain on the passivation layer and extending through the first and second through hole to interconnect the first and second active layers, respectively; a first distance defined between a contact surface between the drain a portion of the first active layer located on the embossed portion and a contact surface between the first source and a portion of the first active layer located on the fattened portion is equal to the height of the embossed portion, and a second distance defined between a contact surface between the drain a portion of the second active layer located on the embossed portion and a contact surface between the second source and a portion of the second active layer located on the fattened portion is equal to the height of the embossed portion as well.

### Claim 14 (depends on 5)

The method of manufacturing a thin film transistor recited in claim 5, wherein a method of forming the first source and the second source comprises: forming the first source located on the first active layer extending to the flattened portion, and forming the second source located on the second active layer extending to the flattened portion;
and wherein a method of forming the first and second through holes comprises: forming the first and second through holes exposing the first and second active layers located on the embossed portion.

### Claim 15 (depends on 5)

The method of manufacturing a thin film transistor recited in claim 5, wherein the method of forming the first source and the second source comprises: forming the first source located on the first active layer on the embossed portion, and forming the second source located on the second active layer on the embossed portion;
and wherein the method of forming the first and second through holes comprises: forming the first and second through holes exposing the first and second active layers located on the flattened portion.

### Claim 16 (depends on 5)

The method of manufacturing a thin film transistor recited in claim 5, wherein the method of forming the first source and the second source comprises: forming the first source located between the flattened portion and the first active layer extending to the flattened portion, and forming the second source located between the flattened portion and the second active layer extending to the flattened portion;
and wherein the method of forming the first and second through holes comprises: forming the first and second through holes exposing the first and second active layers located on the embossed portion.