# US 10,312,375 B2 · Thin-film transistor, method for producing thin-film transistor and image display apparatus using thin-film transistor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,375 B2
- Document ID: US10312375B2
- Status: Granted
- Kind: B2
- Application number: 15/714,393
- Filed: 2017-09-25
- Published: 2018-01-25
- Granted: 2019-06-04
- Earliest claimed: 2015-03-25
- Assignees: Toppan Printing Co., Ltd.
- Applicants: Toppan Printing Co., Ltd.
- Inventors: Noriaki Ikeda; Makoto Nishizawa
- Web page: https://patentgrep.com/patent/US10312375B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G02F 1/136: Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit (G02F1/135 takes precedence)
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 86/021: {of multiple TFTs}
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10P 14/40: of conductive or resistive materials
- H10W 20/01: {Manufacture or treatment}
- H10W 20/48: Insulating materials thereof
- H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate}
- H10K 59/125: including organic TFTs [OTFT]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A thin-film transistor including an insulative substrate, a gate electrode formed on the insulative substrate, a gate insulating layer formed on the substrate and the gate electrode, a source electrode and a drain electrode forming on the gate insulating layer and spaced from each other, a semiconductor layer formed on the gate insulating layer and connected to the source electrode and the drain electrode, a semiconductor protective layer formed on the semiconductor layer, an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer, the interlayer insulating film including a fluorine compound, and an upper electrode formed on the interlayer insulating film.

## Claims

### Claim 1

A thin-film transistor, comprising:
an insulative substrate;
a gate electrode formed on the insulative substrate;
a gate insulating layer formed on the substrate and the gate electrode;
a source electrode and a drain electrode formed on the gate insulating layer and spaced from each other;
a semiconductor layer formed on the gate insulating layer such that the semiconductor layer is connected to the source electrode and the drain electrode;
a semiconductor protective layer formed on the semiconductor layer and comprising a fluorine resin;
an interlayer insulating film formed on the source electrode, the drain electrode and the semiconductor protective layer and comprising an insulative resin material and a non-ionic fluorine-containing surfactant such that a concentration of the non-ionic fluorine-containing surfactant is 10 wt. % or less with respect to the insulative resin material in the interlayer insulating film; and
an upper electrode formed on the interlayer insulating film such that the upper electrode is connected to the drain electrode via electrical conduction formed through the interlayer insulating film.

### Claim 2 (depends on 1)

The thin-film transistor of claim 1, wherein the insulative resin material of the interlayer insulating film is a photosensitive acrylic resin material.

### Claim 3 (depends on 2)

The thin-film transistor of claim 2, wherein the non-ionic fluorine-containing surfactant is dispersed in the interlayer insulating film.

### Claim 4 (depends on 1)

The thin-film transistor of claim 1, wherein the concentration of the non-ionic fluorine-containing surfactant in the interlayer insulating film is 0.05 wt. % or more with respect to the insulative resin material.

### Claim 5 (depends on 2)

The thin-film transistor of claim 2, wherein the concentration of the non-ionic fluorine-containing surfactant in the interlayer insulating film is 0.05 wt. % or more with respect to the insulative resin material.

### Claim 6 (depends on 1)

The thin-film transistor of claim 1, wherein the interlayer insulating film has a relative dielectric constant of 4 or less.

### Claim 7 (depends on 2)

The thin-film transistor of claim 2, wherein the interlayer insulating film has a relative dielectric constant of 4 or less.

### Claim 8 (depends on 1)

The thin-film transistor of claim 1, wherein the insulative resin material of the interlayer insulating film is selected from the group consisting of polymethylmethacrylate, polyvinyl alcohol, polyvinyl phenol, cycloolefin polymer, epoxy resin and polysilsesquioxane.

### Claim 9 (depends on 1)

The thin-film transistor of claim 1, wherein the semiconductor layer comprises one of a low molecular organic semiconductor material, a carbon compound, and a high molecular organic semiconductor material.

### Claim 10 (depends on 2)

The thin-film transistor of claim 2, wherein the semiconductor layer comprises one of a low molecular organic semiconductor material, a carbon compound, and a high molecular organic semiconductor material.

### Claim 11 (depends on 1)

The thin-film transistor of claim 1, wherein the upper electrode comprises at least one of a metal material, a conductive metal oxide material, and a conductive polymer.

### Claim 12 (depends on 1)

The thin-film transistor of claim 1, wherein the semiconductor layer comprises an organic semiconductor.

### Claim 13 (depends on 2)

The thin-film transistor of claim 2, wherein the semiconductor layer comprises an organic semiconductor.

### Claim 14 (depends on 1)

The thin-film transistor of claim 1, wherein each of the source electrode and the drain electrode has a surface treated by a self-assembled monolayer including fluorine.

### Claim 15 (depends on 2)

The thin-film transistor of claim 2, wherein each of the source electrode and the drain electrode has a surface treated by a self-assembled monolayer including fluorine.

### Claim 16 (depends on 1)

An image display apparatus, comprising:
the thin-film transistor of claim 1.

### Claim 17

A method of producing a thin-film transistor, comprising:
forming a gate electrode on an insulative substrate;
forming a gate insulating layer on the substrate and the gate electrode;
forming a source electrode and a drain electrode on the gate insulating layer such that the source electrode and the drain electrode are spaced from each other;
forming a semiconductor layer on the gate insulating layer such that the semiconductor layer is connected to the source electrode and the drain electrode;
forming a semiconductor protective layer comprising a fluorine resin on the semiconductor layer;
forming an interlayer insulating film comprising an insulative resin material and a non-ionic fluorine-containing surfactant on the source electrode, the drain electrode and the semiconductor protective layer; and
forming an upper electrode on the interlayer insulating film such that the upper electrode is connected to the drain electrode via electrical conduction formed through the interlayer insulating film,
wherein the forming of the interlayer insulating film comprises applying an insulative resin material solution including the non-ionic fluorine-containing surfactant on the source electrode, the drain electrode and the semiconductor protective layer such that a concentration of the non-ionic fluorine-containing surfactant is 10 wt. % or less with respect to the insulative resin material in the interlayer insulating film.

### Claim 18 (depends on 17)

The method of claim 17, wherein the semiconductor protective layer comprises a fluorine resin.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
treating a surface of the source electrode by a self-assembled monolayer including fluorine.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
treating a surface of the drain electrode by a self-assembled monolayer including fluorine.
