# US 10,312,373 B2 · Field-effect transistor (FET) having oxide insulating layer disposed on gate insulating film and between source and drain electrodes, and display element, display and system including said FET, and method of manufacturing said FET

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- Number: US 10,312,373 B2
- Document ID: US10312373B2
- Status: Granted
- Kind: B2
- Application number: 15/349,211
- Filed: 2016-11-11
- Published: 2017-05-18
- Granted: 2019-06-04
- Earliest claimed: 2015-11-17
- Assignees: Ricoh Company, Ltd.
- Applicants: Sadanori Arae; Naoyuki Ueda; Yuki Nakamura; Yukiko Abe; Shinji Matsumoto; Yuji Sone; Ryoichi Saotome; Minehide Kusayanagi
- Inventors: Sadanori Arae; Naoyuki Ueda; Yuki Nakamura; Yukiko Abe; Shinji Matsumoto; Yuji Sone; Ryoichi Saotome; Minehide Kusayanagi
- Web page: https://patentgrep.com/patent/US10312373B2

## CPC

- H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/6928: {the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides}
- H10P 50/282: {of inorganic materials}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- G09G 3/3406: {Control of illumination source (illumination devices structurally associated with liquid crystal cells G02F1/1336)}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- H10K 59/1213: {the pixel elements being TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

A field-effect transistor includes a gate electrode, a source electrode and a drain electrode to take out electric current according to an application of a voltage to the gate electrode, a semiconductor layer disposed adjacent to the source electrode and the drain electrode, the semiconductor layer forming a channel between the source electrode and the drain electrode, a first insulating layer as gate insulating film disposed between the semiconductor layer and the gate electrode, and a second insulating layer covering at least a part of a surface of the semiconductor layer, the second insulating layer including an oxide including silicon and alkaline earth metal.

## Claims

### Claim 1

A field-effect transistor comprising:
a gate electrode;
a source electrode and a drain electrode;
a semiconductor layer disposed adjacent to the source electrode and the drain electrode;
a first insulating layer as gate insulating film disposed between the semiconductor layer and the gate electrode; and
a second insulating layer covering at least a part of a surface of the semiconductor layer, the second insulating layer including an oxide including silicon and an alkaline earth metal, wherein molar percent of alkaline earth oxides in the second insulating layer is smaller than molar percent of silicon oxides in the second insulating layer, and wherein the second insulating layer is an etching stopper layer having a form covering at least an area where a channel is formed between the source electrode and the drain electrode.

### Claim 2 (depends on 1)

The field-effect transistor according to claim 1,
wherein the second insulating layer is etched to have a predetermined form.

### Claim 3 (depends on 1)

The field-effect transistor according to claim 1,
wherein a top surface of the semiconductor layer in a lamination direction of a substrate abuts the source electrode and the drain electrode, and
wherein the second insulating layer is disposed at a part of a connection interface between the semiconductor layer and the source electrode and a part of a connection interface between the semiconductor layer and the drain electrode.

### Claim 4 (depends on 1)

The field-effect transistor according to claim 1,
wherein the second insulating layer further includes at least one of aluminum and boron.

### Claim 5 (depends on 1)

The field-effect transistor according to claim 1,
wherein the semiconductor layer is formed of an oxide semiconductor.

### Claim 6 (depends on 1)

A display element comprising:
a drive circuit to output a drive signal, the drive circuit including the field-effect transistor of claim 1; and
a light control element to control light output according to the drive signal from the drive circuit.

### Claim 7 (depends on 6)

The display element according to claim 6,
wherein the light control element includes at least one of an electroluminescent element, an electrochromic element, a liquid crystal element, an electrophoresis element, and an electrowetting element.

### Claim 8 (depends on 6)

A display comprising:
a display unit including multiple display elements, each of which is the display element of claim 6; and
a display control device configured to individually control the multiple display units.

### Claim 9 (depends on 8)

A system comprising:
the display of claim 8; and
an image data generating device to supply image data to the display.

### Claim 10

A method of manufacturing a field-effect transistor, comprising:
forming a first insulating layer as gate insulating film on a gate electrode and a substrate,
forming a semiconductor layer on the first insulating layer, with the first insulating layer interposed between the semiconductor layer and the gate electrode;
forming a second insulating layer covering at least a part of a surface of the semiconductor layer, the second insulating layer including an oxide including silicon and an alkaline earth metal;
covering the semiconductor layer and the second insulating layer to form an electroconductive layer; and
etching the electroconductive layer while using the second insulating layer as an etching stopper to form a source electrode and a drain electrode, adjacent to the semiconductor layer,
wherein molar percent of alkaline earth oxides in the second insulating layer is smaller than molar percent of silicon oxides in the second insulating layer.

### Claim 11 (depends on 10)

The method according to claim 10, further comprising:
forming an initial etching stopper layer on the surface of the semiconductor layer, and etching the initial etching stopper layer to form the second insulating layer, before the step of the etching the electroconductive layer.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the step of etching the second insulating layer is conducted using etching liquid including at least one of ammonium hydrogen fluoride, ammonium fluoride, and hydrogen fluoride.

### Claim 13 (depends on 10)

The method according to claim 10, wherein the step of etching the electroconductive layer is conducted using dry etching.