# US 10,312,371 B2 · Self-aligned shallow trench isolation and doping for vertical fin transistors

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- Number: US 10,312,371 B2
- Document ID: US10312371B2
- Status: Granted
- Kind: B2
- Application number: 15/789,620
- Filed: 2017-10-20
- Published: 2018-02-08
- Granted: 2019-06-04
- Earliest claimed: 2016-06-09
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Fee Li Lie; Junli Wang
- Web page: https://patentgrep.com/patent/US10312371B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/837: {comprising vertical IGFETs}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/20: of masks comprising organic materials
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/066: {the removal being a selective chemical etching step, e.g. selective dry etching through a mask}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

## Claims

### Claim 1

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, comprising:
forming a first vertical fin, a second vertical fin, and a third vertical fin on a substrate surface, wherein three vertical fins are adjacent, and the second vertical fin is between the first vertical fin and the third vertical fin;
removing the second vertical fin to form a fin gap;
forming a pinch-off layer on the first vertical fin, third vertical fin, and the substrate surface between the first vertical fin and third vertical fin, wherein the pinch-off layer has a thickness of less than half the distance between the first vertical fin and the third vertical fin, so a portion of the pinch-off layer on the substrate surface is exposed;
removing the exposed portion of the pinch-off layer to expose the substrate; and
removing at least a portion of the substrate to form an isolation region trench, wherein the distance of a sidewall of the isolation region trench to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising filling the one or more isolation region trenches with a dielectric fill layer to form one or more shallow trench isolation regions.

### Claim 3 (depends on 1)

The method of claim 1, wherein the pinch-off layer is formed on the first vertical fin, third vertical fin, and the substrate surface by atomic layer deposition (ALD).

### Claim 4 (depends on 3)

The method of claim 3, wherein the pinch-off layer has a thickness in the range of about 3 nm to about 10 nm.

### Claim 5 (depends on 4)

The method of claim 4, wherein the thickness of the pinch-off layer is controlled to approximately one monolayer by the ALD.

### Claim 6 (depends on 4)

The method of claim 4, wherein pinch-off layer is silicon oxide.

### Claim 7 (depends on 1)

The method of claim 1, further comprising removing a portion of each of the first and third vertical fins to form two vertical fin segments from each of the first and third vertical fins before forming the pinch-off layer.

### Claim 8 (depends on 7)

The method of claim 7, further comprising removing an exposed portion of the pinch-off layer and at least a portion of the substrate to form an isolation region trench between the two vertical fin segments.

### Claim 9

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, comprising:
forming a plurality of vertical fin segments on a substrate;
forming a pinch-off layer on the plurality of vertical fin segments and the substrate, wherein the pinch-off layer has a thickness on the sidewalls and endwalls of each of the plurality of vertical fin segments, and wherein a portion of the pinch-off layer between at least two of the plurality of vertical fin segments is exposed;
removing the exposed portion of the pinch-off layer to expose an underlying portion of the substrate; and
removing at least a portion of the substrate to form an isolation region trench, where a distance of a sidewall of the isolation region trench to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising filling the isolation region trench with a dielectric fill layer to form a shallow trench isolation region between two vertical fin segments.

### Claim 11 (depends on 10)

The method of claim 10, wherein dielectric fill layer is silicon dioxide (SiO2).

### Claim 12 (depends on 10)

The method of claim 10, wherein the pinch-off layer is formed on the plurality of vertical fin segments by atomic layer deposition (ALD).

### Claim 13 (depends on 10)

The method of claim 10, wherein the pinch-off layer has a thickness in the range of about 0.1 nm to about 25 nm.

### Claim 14 (depends on 10)

The method of claim 10, wherein the isolation region trench has a depth in the range of about 5 nm to about 200 nm.

### Claim 15 (depends on 10)

The method of claim 10, wherein the pinch-off layer is SiO2, SiN, SiON, or TiN.

### Claim 16

A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, comprising:
forming a plurality of vertical fin segments on a substrate;
forming a pinch-off layer on the plurality of vertical fin segments and the substrate, wherein the pinch-off layer has a thickness in the range of about 0.1 nm to about 25 nm on the sidewalls and endwalls of each of the plurality of vertical fin segments, and wherein a portion of the pinch-off layer on the substrate between at least two of the plurality of vertical fin segments is exposed;
removing the exposed portion of the pinch-off layer to expose an underlying portion of the substrate; and
removing at least a portion of the substrate to form an isolation region trench, where a distance of a sidewall of the isolation region trench to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the pinch-off layer is SiO2, SiN, SiON, or TiN.

### Claim 18 (depends on 17)

The method of claim 17, wherein the pinch-off layer is formed on the one or more vertical fin segments by atomic layer deposition (ALD).

### Claim 19 (depends on 17)

The method of claim 17, wherein the isolation region trench has a depth in the range of about 5 nm to about 200 nm.

### Claim 20 (depends on 19)

The method of claim 19, wherein the isolation region trench passes through a doped region to form separate bottom source/drains.