# US 10,312,370 B2 · Forming a sacrificial liner for dual channel devices

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- Number: US 10,312,370 B2
- Document ID: US10312370B2
- Status: Granted
- Kind: B2
- Application number: 15/652,888
- Filed: 2017-07-18
- Published: 2018-03-29
- Granted: 2019-06-04
- Earliest claimed: 2016-09-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Huiming Bu; Kangguo Cheng; Dechao Guo; Sivananda K. Kanakasabapathy; Peng Xu
- Web page: https://patentgrep.com/patent/US10312370B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/011: {comprising FinFETs}
- H10P 50/242: {of Group IV materials}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming fins on a substrate, the fins having a base portion and a top channel portion which includes a liner;
filling an area around the fins with a flowable dielectric;
annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes sidewalls of the base portion of each fin, such that each fin is narrower in the base portion than in the top channel portion; and
etching away the liner to expose the fins and to open gaps that are below a top surface of the solidified dielectric and between sidewalls of the solidified dielectric and sidewalls of respective adjacent fins.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a plurality of said fins from two distinct channel materials.

### Claim 3 (depends on 2)

The method of claim 2, wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.

### Claim 4 (depends on 1)

The method of claim 1, further comprising recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
depositing a gate dielectric layer over the fins and in the gaps; and
depositing a gate over the gate dielectric layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the liner is formed from silicon nitride.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming the fins with an etch that partially etches the substrate.

### Claim 8

A method of forming a semiconductor device, comprising:
forming fins on a substrate, the fins having a base portion and a top channel portion which includes a liner;
filling an area around the fins with a flowable dielectric;
annealing the flowable dielectric to solidify the flowable dielectric, wherein the anneal oxidizes sidewalls of the base portion of each fin, such that each fin is narrower in the base portion than in the top channel portion; and
recessing the solidified dielectric to a level below a top level of the liner and above a bottom level of the liner.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a plurality of said fins from two distinct channel materials.

### Claim 10 (depends on 9)

The method of claim 9, wherein a first distinct channel material is silicon and wherein a second distinct channel material is silicon germanium.

### Claim 11 (depends on 8)

The method of claim 8, further comprising etching away the liner to expose the fins and gaps at sidewalls of the one or more channel fins.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
depositing a gate dielectric layer over the fins and in the gaps; and
depositing a gate over the gate dielectric layer.

### Claim 13 (depends on 8)

The method of claim 8, wherein the liner is formed from silicon nitride.

### Claim 14 (depends on 8)

The method of claim 8, further comprising forming the fins with an etch that partially etches the substrate.