# US 10,312,369 B2 · Semiconductor Fin FET device with epitaxial source/drain

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- Number: US 10,312,369 B2
- Document ID: US10312369B2
- Status: Granted
- Kind: B2
- Application number: 15/837,826
- Filed: 2017-12-11
- Published: 2018-04-12
- Granted: 2019-06-04
- Earliest claimed: 2015-09-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Li Chiang; Cheng-Yi Peng; Jyh-Cherng Sheu; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US10312369B2

## CPC

- H10D 30/798: {being provided in or under the channel regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first fin structure disposed over the substrate and including a first channel region and a first source/drain region;
a second fin structure disposed over the substrate and including a second channel region and a second source/drain region;
a gate structure disposed over at least a portion of the first fin structure and the second fin structure, the first and second channel regions being beneath the gate structure and the first and second source/drain regions being outside of the gate structure;
a first strain material layer disposed over the first source/drain region and a second strain material layer disposed over the second source/drain region, the first and second strain material layers providing stress to the first and second channel regions, respectively;
a contact layer disposed over the first and second strain material layers; and
an insulating layer separating the gate structure and the contact layer,
wherein the first strain material layer is separated from the second strain material layer,
wherein the first and second fin structures further include mask layers under the insulating layer and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the first fin structure further includes a first well region below the first channel region and the second fin structure further includes a second well region below the second channel region, and
the first and second channel regions are made of a different material from the first and second well regions.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first and second strained material layers are selectively grown over the first and second source/drain regions, respectively, to cover surface of sidewalls and top surface of the first and second source/drain regions along different crystal orientations including <100>, <110>, and <101>.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising an interconnect layer filling an opening over the contact layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the interconnect layer contacts side surfaces of one of the source/drain regions.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the interconnect layer is formed of a conductive material including at least one of copper, tungsten, nickel, and titanium.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a width of the first source/drain region is 40% to 60% of a width of the first channel.

### Claim 8

A semiconductor device, comprising:
a substrate;
a first fin structure disposed over the substrate and including a first channel region and a first source/drain region;
a second fin structure disposed over the substrate and including a second channel region and a second source/drain region;
a gate structure disposed over at least a portion of the first fin structure and the second fin structure, the first and second channel regions being beneath the gate structure and the first and second source/drain regions being outside of the gate structure;
a first strain material layer disposed over the first source/drain region and a second strain material layer disposed over the second source/drain region, the first and second strain material layers providing stress to the first and second channel regions, respectively;
a contact layer disposed over the first and second strain material layers; and
an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer, respectively, and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the first fin structure further includes a first well region below the first channel region and the second fin structure further includes a second well region below the second channel region, and
the first and second channel regions are made of a different material from the first and second well regions.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, further comprising an insulating layer separating the gate structure and the contact layer,
wherein the first and second fin structures further include mask layers under the insulating layer and do not have the mask layers in the first and second channel regions and the first and second source/drain regions.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first and second strained material layers are selectively grown over the first and second source/drain regions, respectively, to cover surface of sidewalls and top surface of the first and second source/drain regions along different crystal orientations including <100>, <110>, and <101>.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising an interconnect layer filling in an opening over the contact layer.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the interconnect layer contacts side surfaces of one of the source/drain regions.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the interconnect layer is formed of a conductive material including at least one of copper, tungsten, nickel, and titanium.

### Claim 15 (depends on 8)

The semiconductor device of claim 8, wherein a width of the first source/drain region is 40% to 60% of a width of the first channel.

### Claim 16

A semiconductor device, comprising:
a substrate;
a fin structure disposed over the substrate and including a channel region and a source/drain region;
a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure;
a strain material layer disposed over the source/drain region, the strain material layer providing stress to the channel region;
a contact layer disposed over the strain material layer; and
an insulating layer separating the gate structure and the contact layer,
wherein the fin structure further includes a mask layer under the insulating layer and does not have the mask layer in the channel region and the source/drain region.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising an interconnect layer filling in an opening over the contact layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the interconnect layer contacts side surfaces of one of the source/drain regions.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the interconnect layer is formed of a conductive material including at least one of copper, tungsten, nickel, and titanium.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein a width of the source/drain region is 40% to 60% of a width of the channel.