# US 10,312,368 B2 · High voltage semiconductor devices and methods for their fabrication

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- Number: US 10,312,368 B2
- Document ID: US10312368B2
- Status: Granted
- Kind: B2
- Application number: 15/465,407
- Filed: 2017-03-21
- Published: 2017-07-06
- Granted: 2019-06-04
- Earliest claimed: 2014-07-30
- Assignees: NXP USA, Inc.
- Applicants: NXP USA, Inc.
- Inventors: Philippe Renaud; Zihao M. Gao
- Web page: https://patentgrep.com/patent/US10312368B2

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/834: further characterised by the dopants
- H10D 64/111: {Field plates}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices include a semiconductor substrate containing a source region and a drain region, a gate structure supported by the semiconductor substrate between the source region and the drain region, a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range, and a well region in the semiconductor substrate. The well region has a second conductivity type and is configured to form a channel therein under the gate structure during operation. Methods for the fabrication of semiconductor devices are described.

## Claims

### Claim 1

A method of fabricating a semiconductor device, the method comprising:
implanting a first dopant having a first conductivity type in a portion of a partially-formed semiconductor substrate to form a portion of a composite drift region;
forming an upper epitaxial layer over the partially-formed semiconductor substrate, wherein a semiconductor substrate includes the partially-formed semiconductor substrate and the upper epitaxial layer;
forming a gate structure over the upper epitaxial layer,
forming an additional portion of the composite drift region by implanting a second dopant having the first conductivity type in the upper epitaxial layer, wherein the composite drift region is aligned with a side of the gate structure upon forming the additional portion of the composite drift region;
forming a source region and a drain region in the semiconductor substrate, wherein the drain region is substantially aligned with the portion of the semiconductor substrate in which the first dopant is implanted, and wherein the composite drift region extends laterally from the drain region to at least the side of the gate structure; and
forming a well region in the semiconductor substrate, the well region configured to form a channel during operation of the semiconductor device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a first epitaxial layer on an original substrate to produce the partially-formed semiconductor substrate; and
wherein forming the composite drift region comprises:
masking at least a portion of the first epitaxial layer; and
implanting the first dopant in at least an unmasked portion of the first epitaxial layer, at least a portion of the unmasked portion being substantially aligned with the drain region.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first dopant implanted in the portion of the partially-formed semiconductor substrate and the second dopant implanted in the upper epitaxial layer are each independently selected from the group consisting of arsenic (As), phosphorus (P), and a combination thereof.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the source region and the drain region comprises implanting dopant into the upper epitaxial layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming the well region comprises implanting dopant into the upper epitaxial layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a sinker region electrically connected to the source region, the sinker region extending through the upper epitaxial layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the composite drift region further comprises conducting a dopant drive procedure after implanting the second dopant in the upper epitaxial layer to merge a region formed by implanting the first dopant with a region formed by implanting the second dopant in the upper epitaxial layer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the dopant drive procedure is configured such that a first lateral section of the composite drift region adjacent to the drain region has a bottom boundary deeper than a bottom boundary of a second section of the composite drift region adjacent to the well region.

### Claim 9

A method of fabricating a semiconductor device, the method comprising:
forming a first epitaxial layer on a semiconductor substrate;
forming a first portion of a composite drift region in the first epitaxial layer;
after forming the first portion of the composite drift region, forming a second epitaxial layer over the first epitaxial layer;
forming a gate structure over the second epitaxial layer;
forming a source region and a drain region in the second epitaxial layer;
after forming the gate structure, forming a second portion of the composite drift region in the second epitaxial layer using a side of the gate structure to align the composite drift region with the gate structure, wherein the composite drift region extends laterally from the drain region to at least the side of the gate structure; and
forming a well region in the second epitaxial layer, the well region configured to form a channel during operation of the semiconductor device.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the second portion of the composite drift region comprises:
conducting a dopant implantation procedure; and
conducting a dopant drive procedure after the dopant implantation procedure to merge the first and second portions of the composite drift region.

### Claim 11 (depends on 10)

The method of claim 10, wherein the dopant drive procedure is configured such that a first lateral section of the composite drift region adjacent to the drain region has a bottom boundary deeper than a bottom boundary of a second section of the composite drift region adjacent to the well region.

### Claim 12 (depends on 9)

The method of claim 9, further comprising forming a sinker region electrically connected to the source region, the sinker region extending through the first and second epitaxial layers.

### Claim 13 (depends on 9)

The method of claim 9, wherein the first portion of the composite drift region is under the drain region.

### Claim 14 (depends on 9)

The method of claim 9, wherein the second portion has a higher dopant concentration level than the first portion.

### Claim 15 (depends on 9)

The method of claim 9 wherein forming the first portion of the composite drift region comprises implanting a plurality of different types of n-type dopant.

### Claim 16 (depends on 15)

The method of claim 15 wherein the n-type dopant is selected from the group consisting of arsenic (As), phosphorus (P), and a combination thereof.