# US 10,312,365 B1 · Laterally diffused MOSFET on fully depleted SOI having low on-resistance

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- Number: US 10,312,365 B1
- Document ID: US10312365B1
- Status: Granted
- Kind: B1
- Application number: 15/887,932
- Filed: 2018-02-02
- Granted: 2019-06-04
- Earliest claimed: 2018-02-02
- Assignees: Avago Technologies International Sales Pte. Limited
- Applicants: Avago Technologies General IP (Singapore) Pte. Ltd.
- Inventors: Qing Liu; Akira Ito; Shom Surendran Ponoth
- Web page: https://patentgrep.com/patent/US10312365B1

## CPC

- H10D 30/657: {having substrates comprising insulating layers, e.g. SOI-LDMOS transistors}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/158: {Dispositions}
- H10P 50/283: {by chemical means}
- H10P 90/1906: {Preparing SOI wafers}
- H10P 90/1914: {using bonding}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 62/159: {Shapes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Laterally diffused MOSFETs on fully depleted SOI are provided. A laterally diffused MOSFET includes a substrate and a first semiconductor layer disposed on the substrate. The laterally diffused MOSFET also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. A second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. A gate node is coupled to the first and second gate regions to apply a gate voltage to the first and second gate regions.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first semiconductor layer disposed on the substrate;
a buried oxide layer disposed on the first semiconductor layer,
a second semiconductor layer disposed on the buried oxide layer, wherein the second semiconductor layer comprises a first gate region, a drain region, and a source region, and wherein the first gate region is positioned between the source and the drain regions;
a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer, wherein the first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer;
a second gate region disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation; and
a gate node coupled to the first gate region and the second gate region and configured to apply a gate voltage to the first gate region and the second gate region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein applying the gate voltage to the second gate region is configured to cause a reduction of resistance of the semiconductor device in an on-state.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the drain region comprises a lightly doped segment and a highly doped segment of a same dopant type, wherein the highly doped segment comprises a larger dopant concentration compared to the lightly doped segment.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the lightly doped segment of the drain region is positioned between the first gate region and the highly doped segment of the drain region.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second semiconductor layer has a first side in contact with the buried oxide layer, and wherein the gate node, a source node, and a drain node are respectively coupled to the first gate region, the source region, and the drain region on a second side of the second semiconductor layer opposite to the first side of the second semiconductor layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a third shallow trench isolation extending from the second semiconductor layer to the first semiconductor layer and disposed between the source region at a second end of the second semiconductor layer and the first semiconductor layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the first shallow trench isolation is configured to isolate the drain region from the first semiconductor layer, and wherein the second shallow trench isolation is extended from the second gate region to the first semiconductor layer, and the third shallow trench isolation is configured to isolate the source region from the first semiconductor layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor layer is a doped well in the substrate.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein applying the gate voltage to the second gate region is configured to increase a magnitude of a drain to source current in an on-state.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the source region, the drain region, the second gate region, and the first semiconductor layer are n-type doped, and wherein first gate region in not doped.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the source region, the drain region, the second gate region, and the first semiconductor layer are p-type doped, and wherein first gate region in not doped.

### Claim 12

A method of creating a laterally diffused MOSFET, comprising:
disposing a first semiconductor layer on a first substrate;
disposing a buried oxide layer on the first semiconductor layer;
disposing a second semiconductor layer on the buried oxide layer;
disposing a first gate region, a drain region, and a source region in the second semiconductor layer, wherein the first gate region is positioned between the source and the drain regions;
disposing a first shallow trench isolation between the drain region at a first end of the second semiconductor layer and the first semiconductor layer;
etching a section of the buried oxide layer next to the first shallow trench isolation and farther from the drain region to create an exposed region on the first semiconductor layer;
disposing a second gate region on the exposed region of the first semiconductor layer between the first shallow trench isolation and a second shallow trench isolation; and
coupling a gate node to the first gate region and the second gate region.

### Claim 13 (depends on 12)

The method of claim 12, wherein the gate node is configured to apply a gate voltage to the first gate region and the second gate region, and wherein applying the gate voltage to the second gate region is configured to cause a reduction of a resistance of the laterally diffused MOSFET in an on-state.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
extending the first shallow trench isolation from the second semiconductor layer to the first semiconductor layer; and
isolating the drain region from the first semiconductor layer by the first shallow trench isolation.

### Claim 15 (depends on 12)

The method of claim 12, wherein the drain region comprises a lightly doped segment and a highly doped segment of a same dopant type, wherein the highly doped segment comprises a larger dopant concentration compared to the lightly doped segment.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
arranging the lightly doped segment of the drain region between the first gate region and the highly doped segment of the drain region.

### Claim 17 (depends on 12)

The method of claim 12, wherein the disposing the buried oxide layer and the disposing the second semiconductor layer further comprise:
growing an oxide layer on a second substrate;
flipping and bonding the second substrate to the first substrate, wherein after bonding the oxide layer is attached to the first semiconductor layer of the first substrate; and
making a cut through a thickness of the second substrate to create, on top of oxide layer, a remaining semiconductor layer, wherein the oxide layer is the buried oxide layer and the remaining semiconductor layer is the second semiconductor layer.

### Claim 18 (depends on 12)

The method of claim 12, further comprising:
disposing a third shallow trench isolation between the source region at a second end of the second semiconductor layer and the first semiconductor layer;
extending the third shallow trench isolation from the second semiconductor layer to the first semiconductor layer; and
isolating the source region from the first semiconductor layer by the third shallow trench isolation.

### Claim 19 (depends on 12)

The method of claim 12, further comprising:
extending the second shallow trench isolation from the second gate region to the first semiconductor layer.

### Claim 20

A method of operating a laterally diffused n-type MOSFET, the laterally diffused n-type MOSFET including a first gate region, a second gate region, a source region, and a drain region, the method comprising:
applying a positive gate voltage above a predetermined threshold voltage to the first gate region and the second gate region, wherein the second gate region is disposed on an exposed region of a first semiconductor layer between a first shallow trench isolation and a second shallow trench isolation, the first shallow trench isolation being between the drain region at a first end of a second semiconductor layer and the first semiconductor layer disposed beneath the second semiconductor layer;
generating an inversion layer in the first gate region based on the applied gate voltage to the first gate region;
generating a back bias based on the applied gate voltage to the second gate region; and
generating a current flow from the drain region to the source region, wherein the current flow is generated based at least on the inversion layer and the back bias.