# US 10,312,364 B2 · Semiconductor device and fabrication method thereof

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- Number: US 10,312,364 B2
- Document ID: US10312364B2
- Status: Granted
- Kind: B2
- Application number: 15/723,186
- Filed: 2017-10-03
- Published: 2019-04-04
- Granted: 2019-06-04
- Earliest claimed: 2017-10-03
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Ching-Wen Hung
- Web page: https://patentgrep.com/patent/US10312364B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/01: Manufacture or treatment
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/80: characterised by the materials
- H10D 62/8303: {Diamond}
- H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10D 62/881: {being a two-dimensional material}
- H10D 62/882: {Graphene}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a first dielectric layer on a substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, a 2D material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer, a gate dielectric layer on the 2D material layer, and a gate electrode on the gate dielectric layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first dielectric layer on the substrate;
a hard mask layer on the first dielectric layer;
a trench in the hard mask layer and the first dielectric layer;
a first source/drain electrode layer on a sidewall of the trench;
a second dielectric layer on the first source/drain electrode layer in the trench;
a second source/drain electrode layer on the second dielectric layer in the trench, wherein both of the first source/drain electrode layer and the second source/drain electrode layer extend along the sidewall and a bottom of the trench;
a third dielectric layer on the second source/drain electrode layer in the trench;
a two-dimensional (2D) material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer;
a gate dielectric layer on the 2D material layer; and
a gate electrode on the gate dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the 2D material layer comprises transition metal dichalcogenide, graphene, or boron nitride.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1 further comprising:
an etch stop layer between the substrate and the first dielectric layer.

### Claim 4 (depends on 3)

The semiconductor device according to claim 3, wherein the first dielectric layer comprises silicon oxide, and the etch stop layer comprises silicon nitride.

### Claim 5 (depends on 3)

The semiconductor device according to claim 3, wherein the first source/drain electrode layer extends vertically along the sidewall of the trench between the 2D material layer and the etch stop layer.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein a top surface of the first source/drain electrode layer is in direct contact with the 2D material layer and a bottom surface of the first source/drain electrode layer is in direct contact with the etch stop layer.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the top surface of the first source/drain electrode layer, a top surface of the second dielectric layer, a top surface of the second source/drain electrode layer, a top surface of the third dielectric layer, and a top surface of the hard mask layer are coplanar.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer completely fill up the trench.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the first source/drain electrode layer is insulated from the second source/drain electrode layer by the second dielectric layer.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the first source/drain electrode layer and the second source/drain electrode layer are ring shaped and are concentrically arranged in the trench around the third dielectric layer.

### Claim 11

A method for fabricating a semiconductor device, comprising:
providing a substrate having thereon an etch stop layer, a first dielectric layer on the etch stop layer, and a hard mask layer on the first dielectric layer;
forming a trench in the hard mask layer and the first dielectric layer;
forming a first source/drain electrode layer on a sidewall of the trench, wherein the first source/drain electrode layer extends along the sidewall and a bottom of the trench;
forming a second dielectric layer to cover the first source/drain electrode layer in the trench;
forming a second source/drain electrode layer on the second dielectric layer in the trench;
forming a third dielectric layer on the second source/drain electrode layer in the trench;
forming a two-dimensional (2D) material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer;
forming a gate dielectric layer on the 2D material layer; and
forming a gate electrode on the gate dielectric layer.

### Claim 12 (depends on 11)

The method for fabricating a semiconductor device according to claim 11 further comprising:
planarizing the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer.

### Claim 13 (depends on 11)

The method for fabricating a semiconductor device according to claim 11, wherein the 2D material layer comprises transition metal dichalcogenide, graphene, or boron nitride.

### Claim 14 (depends on 11)

The method for fabricating a semiconductor device according to claim 11, wherein the first dielectric layer comprises silicon oxide, and the etch stop layer comprises silicon nitride.

### Claim 15 (depends on 11)

The method for fabricating a semiconductor device according to claim 11, wherein the first source/drain electrode layer extends vertically along the sidewall of the trench between the 2D material layer and the etch stop layer.

### Claim 16 (depends on 15)

The method for fabricating a semiconductor device according to claim 15, wherein a top surface of the first source/drain electrode layer is in direct contact with the 2D material layer and a bottom surface of the first source/drain electrode layer is in direct contact with the etch stop layer.

### Claim 17 (depends on 16)

The method for fabricating a semiconductor device according to claim 16, wherein the top surface of the first source/drain electrode layer, a top surface of the second dielectric layer, a top surface of the second source/drain electrode layer, a top surface of the third dielectric layer, and a top surface of the hard mask layer are coplanar.

### Claim 18 (depends on 11)

The method for fabricating a semiconductor device according to claim 11, wherein the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer completely fill up the trench.

### Claim 19 (depends on 11)

The method for fabricating a semiconductor device according to claim 11, wherein the first source/drain electrode layer is insulated from the second source/drain electrode layer by the second dielectric layer.

### Claim 20 (depends on 19)

The method for fabricating a semiconductor device according to claim 19, wherein the first source/drain electrode layer and the second source/drain electrode layer are ring shaped and are concentrically arranged in the trench around the third dielectric layer.