# US 10,312,363 B1 · Semiconductor device having improved edge trench, source electrode and gate electrode structures

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- Number: US 10,312,363 B1
- Document ID: US10312363B1
- Status: Granted
- Kind: B1
- Application number: 15/886,953
- Filed: 2018-02-02
- Granted: 2019-06-04
- Earliest claimed: 2018-02-02
- Assignees: Sanken Electric Co., Ltd.
- Applicants: Sanken Electric Co., Ltd.
- Inventors: Shunsuke Fukunaga; Taro Kondo
- Web page: https://patentgrep.com/patent/US10312363B1

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device may include a device region having one or more active trenches, a field termination region having an edge trench. A depth of the edge trench is larger than a depth of the one or more active trenches. A thickness of an insulation layer in the edge trench is larger than a thickness of an insulation layer in the one or more active trenches. In some embodiments, the first depth is from 1.2 to 2.0 times larger than the second depth, and a first width of the edge trench is 1.5 to 4.0 times larger than a second width of the one or more active trenches. In a cross-sectional view, a gate electrode of the edge trench is laterally offset from the source electrode in a depth direction of the edge trench such that the gate electrode and the source electrode do not overlap.

## Claims

### Claim 1

A semiconductor device, comprising:
a device region comprising one or more active trenches, each having a first gate electrode and a first source electrode separated from each other in a depth direction of the one or more active trenches; and
a field termination region comprising an edge trench having a second gate electrode and a second source electrode separated from each other in a depth direction of the edge trench, wherein
a first depth of the edge trench is larger than a second depth of the one or more active trenches,
a thickness of a first insulation layer between the second gate electrode and an epitaxial layer in the edge trench is larger than a thickness of a second insulation layer between the first gate electrode and the epitaxial layer in the one or more active trenches, and
in a cross-sectional view, the second gate electrode is laterally offset from the second source electrode in the depth direction of the edge trench such that the second gate electrode and the second source electrode do not overlap in the depth direction.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first depth is from 1.2 to 2.0 times larger than the second depth.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein a first width of the edge trench is from 1.5 to 4.0 times larger than a second width of the one or more active trenches.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein a first material of the first insulating layer is different from a second material of the second insulating layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein the first material comprises Si3N4 and the second material comprises SiO2.

### Claim 6

A semiconductor device, comprising:
a device region comprising one or more active trenches, each having a first gate electrode and a first source electrode separated from each other in a depth direction of the one or more active trenches; and
a field termination region comprising an edge trench having a second gate electrode and a second source electrode separated from each other in a depth direction of the edge trench, wherein
a first depth of the edge trench is larger than a second depth of the one or more active trenches,
a thickness of a first insulation layer between the second gate electrode and an epitaxial layer in the edge trench is larger than a thickness of a second insulation layer between the first gate electrode and the epitaxial layer in the one or more active trenches, and
a first pitch between the active trenches and a second pitch between the edge trench and an adjacent one of the active trenches is set such that the second pitch is from 30% to 70% smaller than the first pitch.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein a first material of the first insulating layer is different from a second material of the second insulating layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the first material comprises Si3N4 and the second material comprises SiO2.