# US 10,312,362 B2 · Switching element having inclined body layer surfaces

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- Number: US 10,312,362 B2
- Document ID: US10312362B2
- Status: Granted
- Kind: B2
- Application number: 15/833,938
- Filed: 2017-12-06
- Published: 2018-06-28
- Granted: 2019-06-04
- Earliest claimed: 2016-12-27
- Assignees: Toyota Jidosha Kabushiki Kaisha
- Applicants: Toyota Jidosha Kabushiki Kaisha
- Inventors: Tetsuya Yamada; Takashi Okawa; Tomohiko Mori; Hiroyuki Ueda
- Web page: https://patentgrep.com/patent/US10312362B2

## CPC

- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 12/031: {of IGBTs}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/3416: {Nitrides}
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/646: {of Group III-V materials}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 52/402: {of semiconductor materials}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 12/032: {of vertical IGBTs}
- H10D 12/441: {Vertical IGBTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A switching element includes a semiconductor substrate that includes a first n-type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface. The inclined surface is inclined such that the depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction. The inclined surface is disposed below the gate electrode.

## Claims

### Claim 1

A switching element comprising:
a semiconductor substrate including:
a first n-type semiconductor layer exposed to a surface of the semiconductor substrate;
a p-type body layer constituted by an epitaxial layer exposed to the surface of the semiconductor substrate; and
a second n-type semiconductor layer exposed to the surface of the semiconductor substrate and separated from the first n-type semiconductor layer by the p-type body layer;
a gate insulating film configured to cover a range across a surface of the first n-type semiconductor layer, a surface of the body layer between the first n-type semiconductor layer and the second n-type semiconductor layer, and a surface of the second n-type semiconductor layer; and
a gate electrode configured to face the body layer between the first n-type semiconductor layer and the second n-type semiconductor layer through the gate insulating film,
wherein an interface between the first n-type semiconductor layer and the body layer includes an inclined surface which is not curved, the inclined surface is inclined such that a depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction, and the inclined surface is disposed below the gate electrode, and
the interface includes a surface layer portion interface vertically extending downward from the surface of the semiconductor substrate below the gate electrode, the inclined surface is positioned on a lower side of the surface layer portion interface, and an angle of the inclined surface with respect to the surface of the semiconductor substrate is less than 60°.

### Claim 2 (depends on 1)

The switching element according to claim 1, wherein the surface layer portion interface has an angle with respect to the surface of the semiconductor substrate equal to or greater than 80° and equal to or less than 90°.

### Claim 3 (depends on 1)

The switching element according to claim 1, wherein:
the semiconductor substrate includes at least two body layers and two second n-type semiconductor layers, and
the gate insulating film covers a range across a surface of a spacing portion which is a portion positioned between the two body layers in the first n-type semiconductor layer, a portion of the surface of the p-type body layer which is positioned between the spacing portion and one of the second n-type semiconductor layer, and a portion of the surface of the one second n-type semiconductor layer.