# US 10,312,361 B2 · Trenched vertical power field-effect transistors with improved on-resistance and breakdown voltage

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- Number: US 10,312,361 B2
- Document ID: US10312361B2
- Status: Granted
- Kind: B2
- Application number: 15/344,377
- Filed: 2016-11-04
- Published: 2017-05-04
- Granted: 2019-06-04
- Earliest claimed: 2014-05-15
- Assignees: The Regents of the University of California
- Applicants: The Regents of the University of California
- Inventors: Srabanti Chowdhury; Jeonghee Kim; Chirag Gupta; Stacia Keller; Silvia H. Chan; Umesh K. Mishra
- Web page: https://patentgrep.com/patent/US10312361B2

## CPC

- H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 30/478: {the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body}
- H10D 62/114: {PN junction isolations}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

## Claims

### Claim 1

A vertical transistor, comprising:
a first III-nitride layer on a second III-nitride layer and comprising a lateral channel;
a polar c-plane interface and nonpolar and/or semipolar interfaces between the first III-nitride layer and the second III-nitride layer;
a drift region connected to the lateral channel, the drift region comprising one or more doped Gallium Nitride layers;
a source contact to the lateral channel;
a drain contact to the drift region; and
one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact, wherein:
the polar interface is between the drift region and one or more gates;
the drift region comprises a current blocking structure;
voltage is predominantly held in a vertical direction in an off-state;
the current is channeled through an aperture in the current-blocking structure after it flows from under the one or more gates, into the drift region in an on-state; and
the one or more gates and/or the current blocking structure:
(i) induce a two dimensional electron gas at one or more sidewalls of the gates and/or of the current blocking structure, and/or
(ii) the current blocking structure comprises different material regions that can provide a compensating charge, wherein the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in the off-state.

### Claim 2 (depends on 1)

The device of claim 1, wherein the current-blocking structure is comprised of trenches filled with insulator and metal to provide the compensating charge.

### Claim 3 (depends on 1)

The device of claim 1, wherein the current-blocking structure is comprised of trenches filled with alternating layers of semiconductor material to provide the compensating charge.

### Claim 4 (depends on 1)

The device of claim 1, wherein the device is a III-nitride device.

### Claim 5 (depends on 1)

The device of claim 1, wherein the current blocking structure:
has the one or more sidewalls adjacent to the current carrying region of the drift region, and
is structured such that the one or more sidewalls reduce resistance to the current's flow in the current carrying drift region.

### Claim 6 (depends on 1)

The device of claim 1, comprising:
a part A bonded to a part B, wherein:
the Part A comprises the one or more gates, the source, and the lateral channel;
the Part B comprises the drift region that carries the current flow via a vertical or sloped two-dimensional electron gas (2-DEG) and along the sidewall; and
the current flow from the lateral channel to the drift region is confined substantially to an aperture defined by the current blocking structure.

### Claim 7 (depends on 1)

The device of claim 1, wherein the drift region is a voltage blocking region that can be fully depleted at voltages lower than a desired breakdown voltage.

### Claim 8 (depends on 1)

The device of claim 1, wherein:
the current blocking structure has one or more dimensions and materials, and
the current-carrying region has one or more dimensions and doping, such that:
an electric field held in the current blocking region is less than its breakdown field in the off-state, and
the current-carrying region becomes fully depleted in the off-state, thus enabling a breakdown voltage of the device.

### Claim 9 (depends on 1)

The device of claim 1, wherein, in the on state, the gates deplete the lateral channel adjacent the gates' sidewalls, so that the current flows predominantly from under the gate to the drift region.

### Claim 10 (depends on 1)

The transistor of claim 1, further comprising:
a plurality of trenches in one or more of the III-nitride layers, wherein the trenches shape the lateral channel; and
one of the gates in each of the trenches.

### Claim 11 (depends on 10)

The transistor of claim 10, wherein the source contact forms metal regions between the gates and mitigates high field regions at the gate edges, ensuring the peak field is in the bulk of the device.

### Claim 12 (depends on 10)

The transistor of claim 10, wherein a polarization induced two dimensional electron gas (2DEG) is formed in regions between the trenches, resulting in the 2DEG which spreads the current efficiently in the drift region to make the full chip area active.

### Claim 13 (depends on 12)

The transistor of claim 12, wherein the channel comprising the 2DEG along the vertical non-polar and/or semipolar interfaces is induced only under forward bias on the gates and the 2DEG on the polar c-plane is always present for all operating conditions.

### Claim 14 (depends on 13)

The transistor of claim 13, wherein the non-polar interface includes an m-plane interface.

### Claim 15 (depends on 14)

The transistor of claim 14, wherein the first III-nitride layer is GaN and the second III-nitride layer is AlGaN.

### Claim 16 (depends on 1)

The transistor of claim 1, further comprising:
a dielectric layer between the gates and the lateral channel, or
the dielectric layer between the gates and the second III-nitride layer and along the interfaces; and
wherein the dielectric provides negligible threshold shift under gate voltages between −10 V and +10V.

### Claim 17 (depends on 1)

The transistor of claim 1, wherein the transistor's electrically active device area is equal to a geometric chip area on which the device is formed and a device having an on resistance of 1 mΩcm2 has three times smaller chip area for the same Ron as a 3 mΩcm2 device.

### Claim 18 (depends on 1)

The transistor of claim 1, wherein the transistor is a vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a vertical Junction Field Effect Transistor.

### Claim 19

A method of fabricating a vertical transistor, comprising:
depositing a semiconductor structure including a first III-nitride layer on a second III-nitride layer and comprising a lateral channel, wherein:
a polar c-plane interface and nonpolar and/or semipolar interfaces are between the first III-nitride layer and the second III-nitride layer;
the lateral channel is connected to a drift region;
the drift region comprising one or more doped Gallium Nitride layers;
depositing a source contact to the lateral channel;
depositing a drain contact to the drift region;
depositing one or more gates on the lateral channel and positioned to modulate current flowing vertically from the source contact, through the drift region, and to the drain contact; and
forming a trench region around a current carrying region of the drift region; and wherein:
the polar interface is between the drift region and one or more gates,
the trench region comprises a current blocking structure comprising different material layers that can provide a compensating charge,
the compensating charge can fully deplete an ionized dopant concentration in a current carrying region of the drift region in an off-state,
modulation of a current from a source to a drain occurs in the lateral channel,
voltage is predominantly held in a vertical direction in the off-state, and
the current is channeled through an aperture in the current-blocking structure after it flows from under the gates into the drift region in an on-state.