# US 10,312,360 B2 · Method for producing trench high electron mobility devices

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- Number: US 10,312,360 B2
- Document ID: US10312360B2
- Status: Granted
- Kind: B2
- Application number: 15/412,141
- Filed: 2017-01-23
- Published: 2017-05-11
- Granted: 2019-06-04
- Earliest claimed: 2013-06-18
- Applicants: Stephen P. Barlow
- Inventors: Stephen P. Barlow
- Web page: https://patentgrep.com/patent/US10312360B2

## CPC

- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 30/478: {the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/82: Heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2925: {Surface structures}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3216: {Nitrides}
- H10P 14/3416: {Nitrides}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10P 30/206: {into Group III-V semiconductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a silicon substrate and depositing a photoresist material there-over, removing a predetermined portion first dielectric layer to define an exposed portion, implanting dopants into the exposed portion to define a doped portion, preferentially removing silicon from the exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a silicon face having a 111 orientation, and forming a 2DEG on at least one sidewall.

## Claims

### Claim 1

A method for producing a solid-state device, comprising: a) on a silicon substrate having a substantially flat topside and a substantially flat, oppositely disposed bottomside, forming a first dielectric layer over an epitaxial layer at least partially covering the topside; b) depositing a photoresist material over the first dielectric layer; c) removing a predetermined portion of the photoresist material to define a negative photoresist pattern; d) removing a predetermined portion of the first dielectric layer corresponding to the negative photoresist pattern to define an exposed portion; e) implanting dopants into the exposed portion to define a doped portion; f) removing silicon from a second exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls defining the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a silicon face having a 111 orientation, and wherein the first dielectric is removed prior to the removal of silicon from the second exposed portion; g) removing remaining first dielectric layer; h) forming a 2DEG on at least one sidewall; i) depositing a second dielectric layer over the at least one sidewall; j) forming a first buffer layer in electric communication with the bottomside; and k) forming at least one ohmic contact in the first buffer layer to define a drain; wherein the first buffer layer is formed before forming the first dielectric layer and prior to forming the epitaxial layer.

### Claim 2 (depends on 1)

The method of claim 1 and further comprising: m) doping the first buffer layer to define a highly doped buffer layer; n) applying gate oxides to define gate regions; p) applying a passivation layer; q) activating the respective dopants; r) annealing the silicon substrate; wherein the passivation layer is between about 0.4 micron and about 2 microns thick.

### Claim 3 (depends on 2)

The method of claim 2 wherein the doped portion has a dopant concentration of between about 1013 dopants per cubic centimeter and about 1018 dopants per cubic centimeter; and wherein the highly doped buffer layer has a dopant concentration of between about 1018 dopants per cubic centimeter and about 1020 dopants per cubic centimeter.

### Claim 4 (depends on 2)

The method of claim 2 wherein the highly doped buffer layer is between about 1 micron thick and about 3 microns thick; wherein the passivation layer is between about 0.4 micron thick and about 0.8 microns thick; and wherein the first dielectric layer is between about 1 Angstrom unit thick and about 10 microns thick.

### Claim 5 (depends on 1)

The method of claim 1 wherein the first buffer layer begins between 10 microns and 800 microns from the bottomside.

### Claim 6

A method for producing a transistor device, comprising: a) on a silicon substrate having a substantially flat topside and a substantially flat, oppositely disposed bottomside, forming a first dielectric layer over an epitaxial layer at least partially covering the topside; b) depositing a photoresist material over the first dielectric layer; c) removing a predetermined portion of the photoresist material to define a negative photoresist pattern; d) removing a predetermined portion of the first dielectric layer corresponding to the negative photoresist pattern to define an exposed portion; e) implanting dopants into the exposed portion to define a doped portion; f) removing silicon from a second exposed portion to generate trenches having V-shaped cross-sections and having first and second angled sidewalls intersecting to define the V-shaped cross-section, wherein each angled sidewall defining the V-shaped cross-section is a silicon face having a 111 orientation and wherein the first dielectric is removed before removing silicon from the second exposed portion; g) removing remaining first dielectric layer; hi) applying a growth promoter to the at least one sidewall; h2) after hi), applying a stress buffer layer to the at least one sidewall; h3) after h2), forming a first GaN layer on the at least one sidewall; h4) after h3), forming an Al0.27Ga0.73N layer over the first GaN layer; h5) after h4), forming a second GaN layer over the Al0.27Ga0.73N layer to yield a 2DEG layer; i) depositing a third dielectric layer over the at least one sidewall; j) forming a first buffer layer in electric communication with the bottomside; k) forming at least one ohmic contact in the first buffer layer to define a Drain; l) depositing a second dielectric layer to fill in trenches and planarize the silicon substrate; m) doping the first buffer layer to define a highly doped buffer layer; n) applying gate oxides to predetermined portions of the topside to define Gate regions; o) applying a first metallization layer over predetermined portions of the topside to define source regions; p) applying a passivation layer over the first metallization layer; r) activating the respective dopants; s) applying a second metallization layer over the bottomside; and t) after s), annealing the substrate; wherein the doped portion has a dopant concentration of between about 1013 dopants per cubic centimeter and about 1018 dopants per cubic centimeter; wherein the highly doped buffer layer has a dopant concentration of between about 1018 dopants per cubic centimeter and about 1020 dopants per cubic centimeter; wherein the highly doped buffer layer is between about 1 micron thick and about 3 microns thick; wherein the passivation layer is between about 0.4 micron thick and about 0.8 microns thick; wherein the first dielectric layer is between about 1 Angstrom unit thick and about 10 microns thick; and wherein the first dielectric material is selected from the group including SiO2, Si3N4, and combinations thereof; wherein the first buffer layer is formed before forming the first dielectric layer and prior to forming the epitaxial layer.

### Claim 7 (depends on 6)

The method of claim 6 wherein the at least one ohmic contact is disposed at the intersection of the first and second angled sidewalls and wherein the ohmic contact extends into the first buffer layer.