# US 10,312,359 B2 · Guard rings for cascode gallium nitride devices

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- Number: US 10,312,359 B2
- Document ID: US10312359B2
- Status: Granted
- Kind: B2
- Application number: 15/955,555
- Filed: 2018-04-17
- Published: 2018-08-23
- Granted: 2019-06-04
- Earliest claimed: 2016-07-12
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Woochul Jeon; Chun-Li Liu; Ali Salih
- Web page: https://patentgrep.com/patent/US10312359B2

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/411: {for FETs}
- H10D 84/84: Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 70/465: {Bumps or wires}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

## Claims

### Claim 1

A semiconductor device comprising:
a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gates;
an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and
a gate bus formed as a guard ring of the D-mode transistor;
wherein the gate bus is coupled with one or more gate pads of the D-mode transistor; and
wherein the one or more gate pads of the D-mode transistor couple with the source pads of the E-mode transistor and an electrical ground.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT).

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the E-mode transistor is a silicon (Si) field effect transistor (FET).

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a second guard ring surrounding an outer perimeter of the guard ring of the D-mode transistor.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a pin out from each of the drain of the D-mode transistor and the gate and the source of the E-mode transistor.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the source of the D-mode transistor is coupled to the drain of the E-mode transistor.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the source of the D-mode transistor and the drain of the E-mode transistor are coupled together through a wire bond.

### Claim 9

A semiconductor device comprising:
a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gates;
an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and
a gate bus formed as a guard ring of the D-mode transistor;
wherein the gate bus is coupled with one or more gate pads of the D-mode transistor; and
wherein the one or more gate pads of the D-mode transistor couple with the source pads of the E-mode transistor and an electrical ground; and
wherein the source is not grounded.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT).

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the E-mode transistor is a silicon (Si) field effect transistor (FET).

### Claim 12 (depends on 9)

The semiconductor device of claim 9, further comprising a second guard ring surrounding an outer perimeter of the guard ring of the D-mode transistor.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, further comprising a pin out from each of the drain of the D-mode transistor and the gate and the source of the E-mode transistor.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein the source of the D-mode transistor is coupled to the drain of the E-mode transistor.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein the source of the D-mode transistor and the drain of the E-mode transistor are coupled together through a wire bond.

### Claim 17

A semiconductor device comprising:
a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gates;
an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and
a gate bus formed as a guard ring of the D-mode transistor;
a second guard ring surrounding an outer perimeter of the first guard ring;
wherein the gate bus is coupled with one or more gate pads of the D-mode transistor; and
wherein the one or more gate pads of the D-mode transistor couple with the source pads of the E-mode transistor and an electrical ground.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a channel between the gate bus and the second guard ring is depleted.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein a channel between the gate bus and the second guard ring is active.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame.