# US 10,312,358 B2 · High electron mobility transistors with improved heat dissipation

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- Number: US 10,312,358 B2
- Document ID: US10312358B2
- Status: Granted
- Kind: B2
- Application number: 15/516,536
- Filed: 2015-10-02
- Published: 2017-10-12
- Granted: 2019-06-04
- Earliest claimed: 2014-10-02
- Assignees: University of Florida Research Foundation, Inc.
- Applicants: University of Florida Research Foundation, Incorporated
- Inventors: Fan Ren; Stephen John Pearton; Mark E. Law; Ya-Hsi Hwang
- Web page: https://patentgrep.com/patent/US10312358B2

## CPC

- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10W 40/10: Arrangements for heating
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

III-nitride based high electron mobility transistors (HEMTs), such as AlGaN/GaN HEMTs on Silicon substrates, with improved heat dissipation are described herein. A semiconductor device having improved heat dissipation may include a substrate having a top surface and a bottom surface, a nucleation layer on the top surface of the substrate, a transition layer on the nucleation layer, a buffer layer on the transition layer, a barrier layer on the buffer layer, and a metal layer filling a via hole that extends from the bottom surface of the substrate to a bottom surface of the transition layer.

## Claims

### Claim 1

A semiconductor device having improved heat dissipation, comprising:
a substrate including a top surface and a bottom surface;
a nucleation layer on the top surface of the substrate;
a transition layer on top of the nucleation layer;
a buffer layer on top of the transition layer;
a channel layer on top of the buffer layer;
a barrier layer on top of the channel layer;
a gate disposed on the barrier layer;
a via passing through the substrate and the nucleation layer, exposing a bottom of the transition layer, and aligned directly under the gate; and
an electrically conductive metal layer on the bottom surface of the substrate, the metal layer completely filling the via and extending from the bottom surface of the substrate to the bottom of the transition layer above the nucleation layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the barrier layer comprises AlGaN, InAlN or AlN.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the transition layer comprises
AlGaN layers with different aluminum concentrations.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the buffer layer comprises a GaN layer.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the nucleation layer is an AlN or an AlGaN layer.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the substrate comprises silicon or silicon carbide.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the metal layer comprises gold, silver, copper, at least one refractory metal, or a combination thereof.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1, wherein the channel layer and the buffer layer are formed of the same material.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, further comprising a thin interfacial layer on top of the channel layer.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9, wherein the thin interfacial layer comprises AlN and the channel layer comprises GaN.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, further comprising a cap layer on the buffer layer.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein the metal layer further fills a second via extending from the bottom surface of the substrate to a bottom of a metal interconnect pad overlying the barrier layer.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12, wherein the metal interconnect pad is a source connection pad and the metal layer forms a backside source field plate.

### Claim 14 (depends on 12)

The semiconductor device according to claim 12, wherein the metal interconnect pad is a gate connection pad and the metal layer forms a backside gate field plate.

### Claim 15

A method for fabricating high electron mobility transistor (HEMT) with improved heat dissipation, the method comprising:
providing a transistor on a substrate, wherein a nucleation layer is on the top surface of the substrate and a transition layer is on the nucleation layer below the transistor; and
forming a first metal-filled via that extends from a bottom surface of the substrate to a bottom of the transition layer and is aligned directly under a gate of the transistor,
wherein the first metal-filled via is completely filled with an electrically conductive metal layer and passes through the nucleation layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming the first metal-filled via comprises:
etching the substrate to form a first via aligned under the gate of the transistor and exposing the nucleation layer;
etching the exposed nucleation layer through the first via in the substrate, enlarging the first via to extend from the bottom surface of the substrate to the bottom of the transition layer on the nucleation layer; and
filling the first via with the electrically conductive metal layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
etching a second via in the substrate under a metal interconnect pad, extending from the bottom surface of the substrate to a bottom surface of the metal interconnect pad; and
filling the second via with the electrically conductive metal layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the metal interconnect pad is a source connection pad.

### Claim 19 (depends on 17)

The method of claim 17, wherein the metal interconnect pad is a gate connection pad.