# US 10,312,356 B1 · Heterojunction bipolar transistors with multiple emitter fingers and undercut extrinsic base regions

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- Number: US 10,312,356 B1
- Document ID: US10312356B1
- Status: Granted
- Kind: B1
- Application number: 16/013,363
- Filed: 2018-06-20
- Granted: 2019-06-04
- Earliest claimed: 2018-06-20
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Qizhi Liu; Vibhor Jain; James W. Adkisson; Sarah McTaggart; Mark Levy
- Web page: https://patentgrep.com/patent/US10312356B1

## CPC

- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/135: {Non-interconnected multi-emitter structures}
- H10D 62/136: {of heterojunction BJTs (vertical heterojunction BJTs having one or more non-monocrystalline Group IV elements H10D10/861)}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/281: {Base electrodes for bipolar transistors}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 50/642: {Chemical etching}
- H10P 50/667: {by liquid etching only}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 84/641: {Combinations of only vertical BJTs (vertical complementary BJTs H10D84/673)}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 50/242: {of Group IV materials}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are arranged to surround a plurality of active regions, and a collector is located in each of the active regions. A base layer includes a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions. The first sections of the base layer contain single-crystal semiconductor material, and the second sections of the base layer contain polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a plurality of cavities. A plurality of emitter fingers are respectively arranged on the first sections of the base layer.

## Claims

### Claim 1

A device structure for a heterojunction bipolar transistor, the device structure comprising:
a plurality of trench isolation regions arranged to surround a plurality of active regions;
a collector in each of the active regions;
a base layer including a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions, the first sections of the base layer contain single-crystal semiconductor material, the second sections of the base layer contain polycrystalline semiconductor material, and the second sections of the base layer spaced in a vertical direction from the trench isolation regions to define a plurality of cavities; and
a plurality of emitter fingers respectively arranged on the first sections of the base layer.

### Claim 2 (depends on 1)

The device structure of claim 1 wherein each of the second sections of the base layer includes a silicon-germanium layer that is arranged over one of the trench isolation regions.

### Claim 3 (depends on 2)

The device structure of claim 2 wherein each of the second sections of the base layer includes a silicon layer that is arranged over the silicon-germanium layer of one of the second sections of the base layer.

### Claim 4 (depends on 2)

The device structure of claim 2 wherein each of the first sections of the base layer includes a silicon-germanium layer that is arranged directly over one of the active regions and that laterally adjoins the silicon-germanium layer of one or more of the first sections of the base layer.

### Claim 5 (depends on 1)

The device structure of claim 1 wherein each of the first sections of the base layer includes a silicon layer on one of the active regions, and each of the cavities extends beneath one of the second sections of the base layer to the silicon layer of one of the first sections of the base layer.

### Claim 6 (depends on 5)

The device structure of claim 5 wherein the silicon layer of each first section of the base layer has a thickness, and the cavities have a height that is greater than or equal to the thickness of the silicon layer of each first section of the base layer.

### Claim 7 (depends on 1)

The device structure of claim 1 wherein the first sections of the base layer and the second sections of the base layer adjoin along a plurality of first interfaces, the trench isolation regions adjoin the active regions along a plurality of second interfaces, and each of the first interfaces is arranged directly over one of the second interfaces.

### Claim 8 (depends on 1)

The device structure of claim 1 wherein each of the first sections of the base layer includes a silicon layer arranged on one of the active regions, and each of the cavities includes a first section that extends beneath one of the second sections of the base layer to the silicon layer of one of the first sections of the base layer and a second section that extends into the silicon layer of one of the first sections of the base layer and one of the active regions.

### Claim 9 (depends on 8)

The device structure of claim 8 wherein the second section of each cavity is angled relative to the first section of each cavity.

### Claim 10 (depends on 9)

The device structure of claim 9 wherein each of the trench isolation regions has a top surface, and the second section of each cavity extends to a depth that is below the top surface of each trench isolation region.

### Claim 11 (depends on 1)

The device structure of claim 1 wherein each of the second sections of the base layer include a plurality of openings, and the openings extend through the second sections of the base layer to the cavities.

### Claim 12 (depends on 1)

The device structure of claim 1 further comprising:
an interlayer dielectric layer over the heterojunction bipolar transistor; and
a plurality of contacts extending through the interlayer dielectric layer to the second sections of the base layer.

### Claim 13

A method of forming a heterojunction bipolar transistor, the method comprising:
forming a plurality of trench isolation regions surrounding a plurality of active regions that each include a collector;
forming a base layer that includes a plurality of first sections containing single-crystal semiconductor material that are respectively arranged over the active regions and a second plurality of sections containing polycrystalline semiconductor material that are respectively arranged over the trench isolation regions;
removing a first semiconductor layer of each of the second sections of the base layer selective to a second semiconductor layer of each of the second sections of the base layer to define a plurality of cavities that are arranged in a vertical direction between the second semiconductor layer and the trench isolation regions; and
forming a plurality of emitters respectively arranged on the first sections of the base layer.

### Claim 14 (depends on 13)

The method of claim 13 wherein removing the first semiconductor layer of each of the second sections of the base layer selective to the second semiconductor layer of each of the second sections of the base layer comprises:
forming a plurality of openings that extend through each of the second sections of the base layer to the trench isolation regions.

### Claim 15 (depends on 14)

The method of claim 14 wherein removing the first semiconductor layer of each of the second sections of the base layer selective to the second semiconductor layer of each of the second sections of the base layer further comprises:
after the openings are formed in each second section, isotropically etching the first semiconductor layer.

### Claim 16 (depends on 15)

The method of claim 15 wherein the first semiconductor layer is isotropically etched with a wet chemical etching process.

### Claim 17 (depends on 16)

The method of claim 16 wherein the first semiconductor layer is comprised of silicon, and the second semiconductor layer is comprised of silicon germanium.

### Claim 18 (depends on 16)

The method of claim 16 wherein the first semiconductor layer is completely removed by the wet chemical etching process.

### Claim 19 (depends on 13)

The method of claim 13 wherein each of the first sections of the base layer includes a silicon layer on the respective active region, each of the cavities includes a first section that extends beneath the respective second section of the base layer, and further comprising:
forming a second section of each cavity that extends into the silicon layer of the first section of the base layer and the respective active region,
wherein the second section of each cavity is angled relative to the first section of each cavity.

### Claim 20 (depends on 13)

The method of claim 13 wherein each of the second sections of the base layer includes a third semiconductor layer that is arranged over the second semiconductor layer, the first semiconductor layer has a first conductivity type, and further comprising:
doping the third semiconductor layer of each of the second sections of the base layer to have a second conductivity type,
wherein the first semiconductor layer of each of the second sections of the base layer is removed selective to the third semiconductor layer of each of the second sections of the base layer.