# US 10,312,355 B2 · Tunnel field-effect transistor (TFET) with lateral oxidation

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- Number: US 10,312,355 B2
- Document ID: US10312355B2
- Status: Granted
- Kind: B2
- Application number: 15/833,579
- Filed: 2017-12-06
- Published: 2018-04-19
- Granted: 2019-06-04
- Earliest claimed: 2011-10-14
- Assignees: Board of Regents, The University of Texas System
- Applicants: The Board of Regents of The University of Texas System
- Inventors: Jack C. Lee; Han Zhao
- Web page: https://patentgrep.com/patent/US10312355B2

## CPC

- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6706: {for preventing leakage current (TFTs characterised by the properties of the source or drain H10D30/6713)}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/165: {Tunnel injectors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

## Claims

### Claim 1

A tunnel field-effect transistor (TFET), comprising:
a substrate;
a source region;
a drain region having a first dimension;
a channel region coupled to the drain region;
a tunnel region coupled to the source region and the drain region; and
an oxide region, having a second dimension, wherein:
the oxide region is positioned laterally relative to the source region, wherein:
the source region, the drain region, and the channel region are vertically stacked over the substrate, and
the first dimension of the drain region is equal to the second dimension of the oxide region.

### Claim 2 (depends on 1)

The TFET of claim 1, wherein the first dimension of the drain region includes a width of the drain region, and wherein the second dimension of the oxide region includes a width of the oxide region.

### Claim 3 (depends on 1)

The TFET of claim 1, wherein the first dimension of the drain region includes a depth of the drain region, and wherein the second dimension of the oxide region includes a depth of the oxide region.

### Claim 4 (depends on 1)

The TFET of claim 1, wherein the oxide region is made from a group III-V compound material that has been oxidized.

### Claim 5 (depends on 1)

The TFET of claim 1, wherein the tunnel region includes a portion that is coupled to the channel region, wherein the portion of tunnel region has a third dimension, and wherein the third dimension of the portion of the tunnel region is equal to the second dimension of the oxide region.

### Claim 6 (depends on 1)

The TFET of claim 1, wherein the oxide region is positioned to operate as an insulator to limit an OFF-state leakage current that flows during an OFF-state of the TFET.

### Claim 7 (depends on 1)

The TFET of claim 1, further comprising:
a gate region; and
a passivation layer, wherein the passivation layer is positioned between the tunnel region and the gate region.

### Claim 8 (depends on 7)

The TFET of claim 7, wherein at least one of the drain region, the passivation layer, the channel region, and the tunnel region includes a first compound material, and wherein the source region includes a second compound material.

### Claim 9

A tunnel field-effect transistor (TFET), comprising:
a substrate;
a source region;
a drain region;
a channel region coupled to the drain region;
a tunnel region having a first portion coupled to the channel region;
an oxide region positioned at least partially under the drain region, the channel region, and the first portion of the tunnel region; and
a gate region that overlaps with at least a portion of the channel region and at least a second portion of the tunnel region, wherein:
the drain region, the channel region, the tunnel region, and the source region are made from a first material, and
the substrate is made from a second material different from the first material.

### Claim 10 (depends on 9)

The TFET of claim 9, further comprising:
a gate oxide layer that is positioned between the gate region and one or more of the source region, the tunnel region, the channel region, and the drain region.

### Claim 11 (depends on 9)

The TFET of claim 9, further comprising:
a passivation layer positioned between the tunnel region and the gate region.

### Claim 12 (depends on 11)

The TFET of claim 11, wherein:
the source region is made from a heavily doped compound material of a first conductivity type,
the drain region is made from a heavily doped compound material of a second conductivity type,
the channel region is made from a lightly doped compound material of the second conductivity type,
the tunnel region is made from the heavily doped compound material of the second conductivity type or from another heavily doped compound material of the second conductivity type, and
the first conductivity type is different from the second conductivity type.

### Claim 13 (depends on 12)

The TFET of claim 12, wherein the compound material of the first conductivity type, the compound material of the second conductivity type, and the another compound material of the second conductivity type include group III-V compound materials.

### Claim 14 (depends on 9)

The TFET of claim 9, further comprising:
a source contact and a drain contact, wherein the source region is coupled to the source contact, and wherein the drain region is coupled to the drain contact.

### Claim 15 (depends on 9)

The TFET of claim 9, wherein the oxide region is positioned to operate as an insulator to limit an OFF-state leakage current that flows during an OFF-state of the TFET.

### Claim 16

A tunnel field-effect transistor (TFET), comprising:
a first layer having a first portion and a second portion, wherein the first portion of the first layer includes a source region, and wherein the second portion of the first layer includes an oxide region having a first width;
a second layer that includes a tunnel region, wherein the tunnel region includes a first portion having a second width;
a third layer that includes a channel region; and
a fourth layer that includes a drain region, wherein:
the first width is less than or equal to the second width, and
the oxide region, by virtue of the first width, restricts a path of an OFF-state leakage current that flows in the TFET.

### Claim 17 (depends on 16)

The TFET of claim 16, wherein the oxide region enables an increase in an ON-state current that flows in the TFET.

### Claim 18 (depends on 16)

The TFET of claim 16, further comprising:
a gate region, wherein the gate region is laterally displaced relative to the drain region, and wherein the gate region does not vertically overlie all of the drain region;
a passivation layer positioned between the tunnel region and the gate region; and
a gate oxide layer, wherein the gate oxide layer is positioned between the gate region and any one or more of the source region, the drain region, the channel region, the passivation layer, or the tunnel region.

### Claim 19 (depends on 16)

The TFET of claim 16, wherein the drain region, the channel region, and the tunnel region include a material of a first conductivity type, and wherein the source region includes a material of a second conductivity type.

### Claim 20 (depends on 19)

The TFET of claim 19, wherein the material of the first conductivity type includes an n type material, and wherein the material of the second conductivity type includes a p type material.

### Claim 21 (depends on 16)

The TFET of claim 16, wherein the oxide region is positioned to underlie an entirety of the drain region.

### Claim 22 (depends on 16)

The TFET of claim 16, wherein the fourth layer includes a third width, and wherein the first width of the oxide region is 3% to 30% larger than the third width of the fourth layer.

### Claim 23 (depends on 16)

The TFET of claim 16, wherein the fourth layer includes a third width that is 3% to 30% larger than the first width of the oxide region.