# US 10,312,354 B2 · Method for making thin film transistor

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- Number: US 10,312,354 B2
- Document ID: US10312354B2
- Status: Granted
- Kind: B2
- Application number: 15/851,912
- Filed: 2017-12-22
- Published: 2018-10-18
- Granted: 2019-06-04
- Earliest claimed: 2017-04-13
- Assignees: Tsinghua University; Hon Hai Precision Industry Co., Ltd.
- Applicants: Tsinghua University; Hon Hai Precision Industry Co., Ltd.
- Inventors: Mo Chen; Qun-Qing Li; Li-Hui Zhang; Xiao-Yang Xiao; Jin Zhang; Shou-Shan Fan
- Web page: https://patentgrep.com/patent/US10312354B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 48/031: {of three-or-more electrode devices}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 10/484: {characterised by the channel regions}
- H10K 71/166: {using selective deposition, e.g. using a mask}
- H10P 76/202: {for lift-off processes}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10K 85/221: {Carbon nanotubes}
- H10P 14/3462: {Nanowires}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of making a thin film transistor, the method including: forming a gate insulating layer on a gate electrode; placing a semiconductor layer on the gate insulating layer; locating a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises one nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed in the opening; depositing a conductive film layer on the exposed surface of the semiconductor layer, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, the conductive film layer is divided into two regions, one region is used as a source electrode, the other region is used as a drain electrode.

## Claims

### Claim 1

A method of making a thin film transistor, the method comprising:
providing a gate electrode on a substrate, forming a gate insulating layer on a surface of the gate electrode;
placing a semiconductor layer on the gate insulating layer;
locating a first photoresist layer, a nanowire structure, and a second photoresist layer on the semiconductor layer, and the nanowire structure being sandwiched between the first photoresist layer and the second photoresist layer, wherein the nanowire structure comprises one nanowire;
forming one opening in the first photoresist layer and the second photoresist layer to expose a portion of the surface of the semiconductor layer to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening, and both ends of the nanowire are sandwiched between the first photoresist layer and the second photoresist layer; and
depositing a conductive film layer on the exposed surface of the semiconductor layer using the nanowire structure as a mask, wherein the conductive film layer defines a nano-scaled channel corresponding to the nanowire, and the conductive film layer is divided into two regions by the nano-scaled channel, one region is used as a source electrode, and the other region is used as a drain electrode.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein locating the first photoresist layer, the nanowire structure, and the second photoresist layer on the semiconductor layer comprising:
coating the first photoresist layer on the semiconductor layer;
growing the nanowire structure on a growth substrate;
transferring the nanowire structure from the growth substrate to the first photoresist layer; and
coating the second photoresist layer on the nanowire structure.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein locating the first photoresist layer, the nanowire structure, and the second photoresist layer on the semiconductor layer comprising:
depositing the first photoresist layer on the semiconductor layer;
growing the nanowire structure on a growth substrate;
coating the second photoresist layer on the nanowire structure;
separating the nanowire structure and the second photoresist layer from the growth substrate; and
providing the nanowire structure and the second photoresist layer together on the first photoresist layer.

### Claim 4 (depends on 1)

The method as claimed in claim 1, wherein locating the first photoresist layer, the nanowire structure, and the second photoresist layer on the semiconductor layer comprising:
growing the nanowire structure on a growth substrate;
coating the first photoresist layer on the nanowire structure;
transferring the nanowire structure and the first photoresist layer from the growth substrate to the semiconductor layer; and
depositing the second photoresist layer on the nanowire structure after transferring the nanowire structure and the first photoresist layer.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein the first photoresist layer, the nanowire structure, and the second photoresist layer on the semiconductor layer comprising:
growing a first nanowire structure unit on a first growth substrate;
coating the first photoresist layer on a first nanowire structure unit to form a first preform;
transferring the first preform to the semiconductor layer;
growing a second nanowire structure unit on a second growth substrate;
coating the second photoresist layer on the second nanowire structure unit to form a second preform;
transferring the second preform to the first nanowire structure unit, wherein the first nanowire structure unit and the second nanowire structure unit are in direct contact with each other and form the nanowire structure.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein the nanowire structure comprises a plurality of nanowires parallel to each other.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein the nanowire structure comprises a plurality of nanowires intersected with each other to form a network structure.

### Claim 8 (depends on 1)

The method as claimed in claim 1, wherein a first thickness of the first photoresist layer is in a range of 50 nanometers to 400 nanometers.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein a second thickness of the conductive film layer is less than a first thickness of the first photoresist layer.

### Claim 10 (depends on 1)

The method as claimed in claim 1, wherein forming the opening comprises exposing and removing a portion of the first photoresist layer and a portion of the second photoresist layer to form a patterned photoresist layer.

### Claim 11 (depends on 10)

The method as claimed in claim 10, further comprises removing the patterned photoresist layer and the nanowire structure.

### Claim 12 (depends on 11)

The method as claimed in claim 11, wherein removing the patterned photoresist layer and the nanowire structure comprises placing the patterned photoresist layer in a photoresist removal solution.