# US 10,312,353 B2 · Semiconductor device and method for fabricating the same

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- Number: US 10,312,353 B2
- Document ID: US10312353B2
- Status: Granted
- Kind: B2
- Application number: 16/212,700
- Filed: 2018-12-07
- Published: 2019-04-11
- Granted: 2019-06-04
- Earliest claimed: 2017-08-10
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: En-Chiuan Liou; Yu-Cheng Tung
- Web page: https://patentgrep.com/patent/US10312353B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/80: characterised by the materials
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/853: {comprising FinFETs}
- H10P 14/6923: {the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG}
- H10P 32/141: {the applied layer comprising oxides only}
- H10P 32/1412: {through the applied layer}
- H10P 32/171: {being group IV material}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate having a first region, a second region and a dummy region;
forming a plurality of fins in the first region, the second region and the dummy region;
forming a first solid-state dopant source layer in the first region;
forming a first insulating buffer layer on the first solid-state dopant source layer;
forming a second solid-state dopant source layer in the second region and the dummy region;
forming a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer; and
performing an etch process to cut the fin in the dummy region to form a dummy fin.

### Claim 2 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein forming a first solid-state dopant source layer in the first region further comprises:
masking the first region; and
removing the first solid-state dopant source layer and the first insulating buffer layer from the second region, thereby exposing the fins and the substrate in the second region.

### Claim 3 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein forming a second solid-state dopant source layer in the second region and the dummy region further comprises:
forming the second solid-state dopant source layer on the first region, the second region and the dummy region;
masking the second region and the dummy region; and
removing the second solid-state dopant source layer from the first region, thereby exposing the first insulating buffer layer in the first region.

### Claim 4 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein before performing an etch process to cut the fin in the dummy region, further comprising:
forming a dielectric layer on the first region, the second region and the dummy region;
etching the dielectric layer, the second insulating buffer layer, the first insulating buffer layer, the first solid-state dopant source layer and the second solid-state dopant source layer to a level below a top surface of the fins, thereby exposing a protruding portion of each of the fins; and
diffusing dopants from the first solid-state dopant source layers and second solid-state dopant source layers into the fins respectively in the first region and the second region.

### Claim 5 (depends on 4)

The method for fabricating a semiconductor device according to claim 4, further comprising:
forming a metal gate traversing the fins and covering the dummy region after cutting the fin;
forming source and drain regions in the protruding portions of each of the fins on either side of the metal gate; and
cutting the metal gate into gate segments.

### Claim 6 (depends on 4)

The method for fabricating a semiconductor device according to claim 4, wherein the fin in the dummy region is cut down to a level below the level of the dielectric layer, the second insulating buffer layer, the first solid-state dopant source layer and the second solid-state dopant source layer.

### Claim 7 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein the fin in the dummy region is completely cut and removed.

### Claim 8 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein a top surface of the second insulating buffer layer and a top surface of the second solid-state dopant source layer at both sides of the dummy fins are recessed to a level higher than the remaining dummy fin but lower than the dielectric layer after the cutting, and the top surface of the second insulating butter layer is lower than the top surface of the second solid-state dopant source layer at both sides of the dummy fin after the cutting.

### Claim 9 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein the second solid-state dopant source layer and the second insulating buffer layer at both sides of the dummy fin are completely removed after the cutting so that two grooves are formed respectively between the remaining dummy fin and the dielectric layer at both sides of the dummy fin.