# US 10,312,350 B1 · Nanosheet with changing SiGe percentage for SiGe lateral recess

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- Number: US 10,312,350 B1
- Document ID: US10312350B1
- Status: Granted
- Kind: B1
- Application number: 15/823,684
- Filed: 2017-11-28
- Published: 2019-05-30
- Granted: 2019-06-04
- Earliest claimed: 2017-11-28
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Xin Miao; Wenyu Xu; Chen Zhang
- Web page: https://patentgrep.com/patent/US10312350B1

## CPC

- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6743: {Silicon}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 14/3462: {Nanowires}
- H10P 50/642: {Chemical etching}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein:
the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer; and
a concentration of germanium is varied between each of the plurality of silicon germanium layers;
patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein remaining portions of each of the plurality of silicon germanium layers have the same or substantially the same width as each other;
selectively removing the remaining portions of each of the plurality of silicon germanium layers from the plurality of patterned stacks; and
replacing the removed remaining portions of each of the plurality of silicon germanium layers with respective gate structures;
wherein the concentration of germanium in each of the plurality of silicon germanium layers increases from a top layer to a bottom layer of the plurality of silicon germanium layers in the stacked configuration.

### Claim 2 (depends on 1)

The method according to claim 1, wherein each of the respective gate structures has the same or substantially the same width as each other.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the etching is performed using hydrochloric acid (HCl).

### Claim 4 (depends on 3)

The method according to claim 3, wherein the etching is performed at a temperature of about 400° C. to about 700° C.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising filling vacant areas left by the removed portions of the silicon germanium layers from the lateral sides with a dielectric.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the filling comprises:
conformally depositing a dielectric liner layer on the plurality of patterned stacks and on the substrate; and
removing portions of the dielectric liner layer outside of the vacant areas.

### Claim 7 (depends on 6)

The method according to claim 6, further comprising
growing a plurality of epitaxial source/drain regions between the plurality of patterned stacks, wherein the epitaxial source/drain regions are grown from exposed sides of the plurality of silicon layers in the plurality of patterned stacks.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region.

### Claim 9

A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein:
the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer; and
a concentration of germanium is varied between each of the plurality of silicon germanium layers;
patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein remaining portions of each of the plurality of silicon germanium layers have the same or substantially the same width as each other;
selectively removing the remaining portions of each of the plurality of silicon germanium layers from the plurality of patterned stacks; and
replacing the removed remaining portions of each of the plurality of silicon germanium layers with respective gate structures;
wherein the concentration of germanium in a top layer of the plurality of silicon germanium layers in the stacked configuration is less than the concentration of germanium in a bottom layer of the plurality of silicon germanium layers in the stacked configuration.

### Claim 10

A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer;
patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers;
wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other; and
replacing the remaining portions of each of the plurality of silicon germanium layers with respective gate structures having the same or substantially the same width as each other;
wherein the concentration of germanium in each of the plurality of silicon germanium layers increases from a top layer to a bottom layer of the plurality of silicon germanium layers in the stacked configuration.

### Claim 11 (depends on 10)

The method according to claim 10, wherein the etching is performed using hydrochloric acid (HCl).

### Claim 12 (depends on 10)

The method according to claim 10, further comprising filling vacant areas left by the removed portions of the silicon germanium layers from the lateral sides with a dielectric.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the filling comprises:
conformally depositing a dielectric liner layer on the plurality of patterned stacks and on the substrate; and
removing portions of the dielectric liner layer outside of the vacant areas.

### Claim 14 (depends on 13)

The method according to claim 13, further comprising growing a plurality of epitaxial source/drain regions between the plurality of patterned stacks, wherein the epitaxial source/drain regions are grown from exposed sides of the plurality of silicon layers in the plurality of patterned stacks.

### Claim 15

A method for manufacturing a semiconductor device, comprising:
forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer;
patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other;
etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers;
wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other; and
replacing the remaining portions of each of the plurality of silicon germanium layers with respective gate structures having the same or substantially the same width as each other;
wherein the concentration of germanium in a top layer of the plurality of silicon germanium layers in the stacked configuration is less than the concentration of germanium in a bottom layer of the plurality of silicon germanium layers in the stacked configuration.