# US 10,312,348 B1 · Semiconductor device gate spacer structures and methods thereof

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- Number: US 10,312,348 B1
- Document ID: US10312348B1
- Status: Granted
- Kind: B1
- Application number: 15/891,074
- Filed: 2018-02-07
- Published: 2019-05-23
- Granted: 2019-06-04
- Earliest claimed: 2017-11-22
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuo-Chang Huang; Fu-Peng Lu; Chun-Chang Liu; Chen-Chiu Huang
- Web page: https://patentgrep.com/patent/US10312348B1

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6338: {the reactions being activated by other means than plasma or thermal, e.g. photo-CVD}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 50/648: {Anisotropic liquid etching}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a channel region, the substrate further including a source/drain (S/D) region, the S/D region having a first doped S/D region adjacent to the channel region and a second doped S/D region adjacent to the first doped S/D region, wherein the second doped S/D region is more heavily doped than the first doped S/D region;
a gate stack over the channel region;
a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride;
a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion, the first vertical portion offset from the second doped S/D region and in physical contact with the first doped S/D region, the first horizontal portion in physical contact with both the first doped S/D region and the second doped S/D region; and
a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein:
the seal spacer includes a second vertical portion and a second horizontal portion; and
the first dielectric layer includes a third vertical portion and a third horizontal portion.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein each of the first, second, and third horizontal portions is in physical contact with a top surface of the substrate.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein a topmost point of the second horizontal portion is lower than a topmost point of the first horizontal portion.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a height of the first horizontal portion is substantially the same as a width of the first vertical portion.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein:
the first vertical portion has a first sidewall, the first sidewall being substantially perpendicular to a top surface of the substrate; and
the first horizontal portion has a second sidewall, the second sidewall intersects the first sidewall at an angle less than 45 degrees.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
the first vertical portion has a first sidewall, the first sidewall being substantially perpendicular to a top surface of the substrate; and
the first horizontal portion has a second sidewall and a first top surface interposed between the first sidewall and the second sidewall, the first top surface being substantially perpendicular to the first sidewall.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising:
a second dielectric layer interposed between the gate spacer and the first dielectric layer, the second dielectric layer being above the first horizontal portion, the second dielectric layer and the gate spacer having different material compositions.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the second dielectric layer partially covers the first top surface.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the second sidewall is substantially perpendicular to a top surface of the substrate.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the gate stack includes a polysilicon gate or a metal gate.

### Claim 12

A semiconductor device, comprising:
a substrate having source/drain (S/D) regions with a channel region interposed between the S/D regions;
a gate stack over the channel region;
a dielectric layer covering sidewalls of the gate stack, the dielectric layer including a nitride;
a spacer layer covering sidewalls of the dielectric layer, the spacer layer including an oxide, wherein a sidewall of the spacer layer includes an upper sidewall, a horizontal surface, and an lower sidewall, thereby forming a step profile; and
a contact etch stop (CES) layer covering the sidewall of the spacer layer, the CES layer including a nitride, and
wherein the S/D regions include a first doped S/D region and a second doped S/D region that is more heavily doped than the first doped S/D region, wherein the upper sidewall is directly above the first doped S/D region, and the lower sidewall is directly above the second doped S/D region.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the upper sidewall intersects the horizontal surface, defining an angle between the upper sidewall and the horizontal surface, the angle being in a range from 85 degrees to 95 degrees.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising:
a hard mask layer disposed between the spacer layer and the CES layer, a dielectric constant of the hard mask layer being higher than a dielectric constant of the spacer layer.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein a thickness of the spacer layer ranges from 10% to 70% of a length of the channel region.

### Claim 16

A method, comprising:
forming a gate structure on a substrate;
forming a seal spacer covering the gate structure and a portion of the substrate;
removing a portion of the seal spacer to expose the portion of the substrate;
forming a gate spacer covering the seal spacer and directly on the exposed portion of the substrate, the gate spacer having a first vertical portion and a first horizontal portion;
forming a hard mask layer covering the gate spacer, the hard mask layer having a second vertical portion and a second horizontal portion;
removing the second horizontal portion of the hard mask layer and part of the first horizontal portion of the gate spacer that is under the second horizontal portion of the hard mask layer; and
forming a contact etch stop (CES) layer covering the gate spacer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
prior to the forming of the CES layer, removing the second vertical portion of the hard mask layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the gate spacer has the lowest dielectric constant in the group of the seal spacer, the gate spacer, the hard mask layer, and the CES layer.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the upper sidewall physically contacts the first doped S/D region and the lower sidewall physically contacts the second doped S/D region.

### Claim 20 (depends on 1)

The semiconductor device of claim 1, wherein the seal spacer physically contacts the gate stack,
wherein the gate spacer physically contacts the seal spacer, and
wherein the first dielectric layer physically contacts the gate spacer.