# US 10,312,347 B2 · Sloped finFET with methods of forming same

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- Number: US 10,312,347 B2
- Document ID: US10312347B2
- Status: Granted
- Kind: B2
- Application number: 15/868,274
- Filed: 2018-01-11
- Published: 2018-06-07
- Granted: 2019-06-04
- Earliest claimed: 2015-02-06
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Edward J. Nowak
- Web page: https://patentgrep.com/patent/US10312347B2

## CPC

- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments of the present disclosure provide an integrated circuit (IC) structure, which can include: a semiconductor fin; a gate dielectric positioned above a first region of the semiconductor fin; a spacer positioned above a second region of the semiconductor fin and adjacent to the gate dielectric; and a source/drain region contacting a third region of the semiconductor fin; wherein the first region of the semiconductor fin includes substantially vertical sidewalls, and the third region of the semiconductor fin includes sloped sidewalls.

## Claims

### Claim 1

A method of forming an integrated circuit (IC) structure, the method comprising:
forming a sacrificial gate on a semiconductor fin;
forming a first spacer on the semiconductor fin, the first spacer positioned circumferentially about the sacrificial gate;
forming a second spacer on the semiconductor fin, the second spacer positioned circumferentially about the first spacer; and
tapering an exposed portion of the semiconductor fin to form sloped sidewalls thereon, the exposed portion of the semiconductor fin positioned adjacent the sacrificial gate, the first spacer, and the second spacer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming one of a source contact and a drain contact on the sloped sidewalls of the semiconductor fin after the forming of the second spacer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a dielectric layer on the sacrificial gate, the first spacer, and the second spacer; and
removing a portion of the dielectric layer to expose the sacrificial gate.

### Claim 4 (depends on 3)

The method of claim 3, further comprising:
selectively removing the sacrificial gate from the semiconductor fin; and
forming a gate dielectric on an exposed first region of the semiconductor fin after the removing of the sacrificial gate.

### Claim 5 (depends on 4)

The method of claim 4, further comprising reducing a width of the exposed first region of the semiconductor fin before the forming of the gate dielectric.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sloped sidewalls are oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

### Claim 7 (depends on 1)

The method of claim 1, wherein the tapering of the exposed portion of the semiconductor fin occurs before the forming of the first spacer and the second spacer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the sacrificial gate comprises a polycrystalline silicon material.

### Claim 9 (depends on 1)

The method of claim 1, wherein the semiconductor fin comprises at least one of a plurality of semiconductor fins positioned on an insulator layer.

### Claim 10

A method of forming an integrated circuit (IC) structure, the method comprising:
forming a sacrificial gate on a semiconductor fin;
forming a first spacer on the semiconductor fin, the first spacer positioned circumferentially about the sacrificial gate;
forming a second spacer on the semiconductor fin, the second spacer positioned circumferentially about the first spacer;
tapering an exposed portion of the semiconductor fin to form sloped sidewalls thereon, the exposed portion of the semiconductor fin positioned adjacent the sacrificial gate, the first spacer, and the second spacer;
and
forming one of a source contact and a drain contact on the sloped sidewalls of the semiconductor fin.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a dielectric layer on the sacrificial gate, the first spacer, and the second spacer; and
removing a portion of the dielectric layer to expose the sacrificial gate.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
selectively removing the sacrificial gate from the semiconductor fin; and
forming a gate dielectric on an exposed first region of the semiconductor fin after the removing of the sacrificial gate.

### Claim 13 (depends on 12)

The method of claim 12, further comprising reducing a width of the exposed first region of the semiconductor fin before the forming of the gate dielectric.

### Claim 14 (depends on 10)

The method of claim 10, wherein the sloped sidewalls are oriented at an angle of between approximately seventy degrees and approximately eighty-seven degrees relative to an insulator layer positioned beneath the IC structure.

### Claim 15 (depends on 10)

The method of claim 10, wherein the tapering of the exposed portion of the semiconductor fin occurs before the forming of the first spacer and the second spacer.

### Claim 16 (depends on 10)

The method of claim 10, wherein the sacrificial gate comprises a polycrystalline silicon material.

### Claim 17 (depends on 10)

The method of claim 10, wherein the semiconductor fin comprises at least one of a plurality of semiconductor fins positioned on an insulator layer.

### Claim 18 (depends on 10)

The method of claim 10, wherein forming the first spacer includes:
covering a portion of a region of the semiconductor fin, the region of the semiconductor fin including an initial geometry of the semiconductor fin.

### Claim 19 (depends on 18)

The method of claim 18, wherein forming the second spacer includes:
covering a remaining portion of the region of the semiconductor fin.

### Claim 20 (depends on 10)

The method of claim 10, wherein forming one of the source contact and the drain contact on the sloped sidewalls of the semiconductor fin further includes:
forming the source contact on the sloped sidewalls of the semiconductor fin, the source contact formed outside of the first spacer and the second spacer; and
forming the drain contact on the sloped sidewalls of the semiconductor fin, opposite the source contact, the drain contact formed outside of the first spacer and the second spacer.