# US 10,312,346 B2 · Vertical transistor with variable gate length

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- Number: US 10,312,346 B2
- Document ID: US10312346B2
- Status: Granted
- Kind: B2
- Application number: 15/297,418
- Filed: 2016-10-19
- Published: 2018-04-19
- Granted: 2019-06-04
- Earliest claimed: 2016-10-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Brent A. Anderson; Bassem M. Hamieh; Stuart A. Sieg; Junli Wang
- Web page: https://patentgrep.com/patent/US10312346B2

## CPC

- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming a plurality of fins on a substrate. The method further includes forming a plurality of deep trenches in the substrate and interposed between each fin of the plurality of fins. The method further includes forming a doped semiconductor layer having a uniform thickness, wherein the doped semiconductor layer is formed prior to removing any fins of the plurality of fins.

## Claims

### Claim 1

A method of forming a vertical transistor, the method comprising of:
patterning a hardmask layer on a semiconductor substrate;
transferring the patterned hardmask layer into the semiconductor substrate, wherein transferring comprises etching a plurality of trenches into the semiconductor substrate to define a plurality of fins at a constant pattern density, the plurality of fins comprising dummy fins;
forming a bottom spacer layer without having to remove the patterned hardmask layer, wherein the bottom spacer layer has a uniform thickness between the plurality of fins, wherein the bottom spacer layer comprises silicon nitride (SiN);
forming an oxide layer on the bottom spacer layer to a top surface of the patterned hardmask layer on the plurality of fins;
removing the dummy fins and forming a plurality of deep trenches into the semiconductor substrate at locations of the dummy fins, wherein removing the dummy fins provides the plurality of fins with a variable pattern density; and
depositing a dielectric material to a top surface of the patterned hardmask layer on the plurality of fins and etching the dielectric material to a top surface of the bottom space layer and form isolation regions of the dielectric material in each of the plurality of deep trenches.

### Claim 2 (depends on 1)

The method of claim 1, wherein the bottom spacer layer is deposited by a high-density plasma (HDP) film deposition process.

### Claim 3 (depends on 1)

The method of claim 1, wherein the bottom spacer layer is deposited with a thickness tolerance less than or equal to 5 nm.

### Claim 4 (depends on 1)

The method of claim 1, wherein the patterned hardmask layer is transferred with a reactive ion etching (RIE) process.