# US 10,312,342 B2 · NEMS devices with series ferroelectric negative capacitor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,342 B2
- Document ID: US10312342B2
- Status: Granted
- Kind: B2
- Application number: 15/695,440
- Filed: 2017-09-05
- Published: 2018-01-11
- Granted: 2019-06-04
- Earliest claimed: 2014-04-30
- Assignees: Purdue Research Foundation
- Applicants: Purdue Research Foundation
- Inventors: Muhammad Ashraful Alam; Muhammad Masuduzzaman; Ankit Jain
- Web page: https://patentgrep.com/patent/US10312342B2

## CPC

- H01G 7/06: having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors (electrets H01G7/02)
- B81B 7/02: containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] (B81B7/04 takes precedence)
- H01G 4/38: Multiple capacitors, i.e. structural combinations of fixed capacitors
- H01G 5/16: using variation of distance between electrodes
- H01G 5/40: Structural combinations of variable capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
- H10B 51/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
- H10B 53/00: Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 64/687: {having cavities, e.g. porous gate dielectrics having gasses therein}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/212: {of only capacitors}
- B81B 2201/014: having a cantilever fixed on one side connected to one or more dimples
- B81B 2201/016: having a bridge fixed on two ends and connected to one or more dimples
- B81B 2201/07: Data storage devices, static or dynamic memories
- H10D 1/68: Capacitors having no potential barriers
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.

## Claims

### Claim 1

A field effect transistor comprising:
a. a source terminal;
b. a drain terminal;
c. a channel separating the source and drain terminals and through which charge carriers flow from the source terminal to the drain terminal, the channel comprising a semiconductor material;
d. a gate electrode; and
e. a gate insulator separating the gate electrode and the channel, the gate insulator comprising a series combination of at least two different negative capacitance (NC) materials, wherein a first one of the NC materials comprises an air gap and a second one of the NC materials comprises a ferroelectric material.

### Claim 2 (depends on 1)

The transistor of claim 1, wherein the transistor is configured as a ferroelectric random access memory device.

### Claim 3 (depends on 1)

The transistor of claim 1, wherein the transistor is configured as a magnetic random access memory device.

### Claim 4 (depends on 1)

The transistor of claim 1, wherein the second one of the NC materials is adjacent to the channel.

### Claim 5 (depends on 4)

The transistor of claim 4, wherein the first one of the NC materials is adjacent to the gate electrode.

### Claim 6 (depends on 5)

The transistor of claim 5, wherein the gate electrode is arranged so that the gate electrode is attached to at least one point in a cantilevered fashion and spaced apart from the second one of the NC materials.

### Claim 7 (depends on 5)

The transistor of claim 5, wherein the gate electrode is mounted to at least two points and spaced apart from the second one of the NC materials.

### Claim 8 (depends on 5)

The transistor of claim 5, wherein the gate electrode comprises a suspended gate.