# US 10,312,337 B2 · Fabrication of nano-sheet transistors with different threshold voltages > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,337 B2 - Document ID: US10312337B2 - Status: Granted - Kind: B2 - Application number: 15/462,372 - Filed: 2017-03-17 - Published: 2018-03-22 - Granted: 2019-06-04 - Earliest claimed: 2016-09-19 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Karthik Balakrishnan; Kangguo Cheng; Pouya Hashemi; Alexander Reznicek - Web page: https://patentgrep.com/patent/US10312337B2 ## CPC - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6743: {Silicon} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/118: {Nanostructure semiconductor bodies} - H10D 62/121: {oriented parallel to substrates} - H10D 64/01: Manufacture or treatment - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 64/671: {the conductor having lateral variation in doping or structure} - H10D 84/0128: {Manufacturing their channels} - H10D 84/0147: {Manufacturing their gate sidewall spacers} - H10D 84/0158: {the components including FinFETs} - H10D 84/0167: {Manufacturing their channels} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 86/01: Manufacture or treatment - H10D 86/011: {comprising FinFETs} - H10P 14/3462: {Nanowires} - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming two or more nano-sheet devices with varying electrical gate lengths, including, forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate, removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layers, where the recess depth is greater than the indentation depth. ## Claims ### Claim 1 A method of forming two or more nano-sheet devices with varying channel lengths, comprising: forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate; removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers; removing a portion of the at least one alternating nano-sheet channel layer in a first of the at least two cut-stacks to form a first recess having a first recess depth in the at least one alternating nano-sheet channel layer; and removing a portion of the at least one alternating nano-sheet channel layer in a second of the at least two cut-stacks to provide two different channel lengths. ### Claim 2 (depends on 1) The method of claim 1, further comprising forming the plurality of sacrificial release layers and the at least one alternating nano-sheet channel layer on the substrate by an epitaxially growth process, patterning and etching the plurality of sacrificial release layers and the at least one alternating nano-sheet channel layer to form a channel stack, and forming a dummy gate on the channel stack. ### Claim 3 (depends on 2) The method of claim 2, wherein the at least two cut-stacks are formed from the same channel stack. ### Claim 4 (depends on 1) The method of claim 1, further comprising forming a mask on at least one of the at least two cut-stacks after removing a portion of the plurality of sacrificial release layers, and removing an additional portion of the plurality of sacrificial release layers from the unmasked cut-stacks. ### Claim 5 (depends on 4) The method of claim 4, wherein the additional portion of the plurality of sacrificial release layers is removed using an isotropic wet etch. ### Claim 6 (depends on 1) The method of claim 1, further comprising foaming a mask on at least one of the at least two cut-stacks before removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the unmasked cut-stacks. ### Claim 7 (depends on 6) The method of claim 6, further comprising removing the mask from the at least one of the at least two cut-stacks after removing a portion of the at least one alternating nano-sheet channel layer, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the previously masked at least one of the at least two cut-stacks and an additional portion of the at least one alternating nano-sheet channel layer from the unmasked at least one of the at least two cut-stacks. ### Claim 8 (depends on 1) The method of claim 1, further comprising forming a source/drain on each of the at least two cut-stacks. ### Claim 9 (depends on 8) The method of claim 8, wherein the source/drains are epitaxially grown on the exposed surfaces of the at least one alternating nano-sheet channel layer. ### Claim 10 A method of forming two or more nano-sheet devices with varying channel lengths, comprising: forming a channel stack including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate; forming at least two cut-stacks from the channel stack, where each of the at least two cut-stacks includes a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer; removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers; forming an indentation fill layer in the indentations; forming a mask on at least one of the two or more cut-stacks; and removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the unmasked cut-stacks. ### Claim 11 (depends on 10) The method of claim 10, further comprising removing the mask from the at least one of the two or more cut-stacks after removing a portion of the at least one alternating nano-sheet channel layer, and removing a portion of the at least one alternating nano-sheet channel layer to form a recess in the previously masked at least one of the two or more cut-stacks and an additional portion of the at least one alternating nano-sheet channel layer from the at least one unmasked of the two or more cut-stacks. ### Claim 12 (depends on 11) The method of claim 11, further comprising forming a source/drain on each of the two or more cut-stacks. ### Claim 13 (depends on 12) The method of claim 12, further comprising forming a gate structure on each of the two or more cut-stacks. ### Claim 14 A method of forming two or more nano-sheet devices with varying channel lengths, comprising: forming at least two cut-stacks including a plurality of sacrificial release layers and at least one alternating nano-sheet channel layer on a substrate; removing a portion of the plurality of sacrificial release layers to form indentations having an indentation depth in the plurality of sacrificial release layers; and removing a portion of the at least one alternating nano-sheet channel layer to form a recess having a recess depth in the at least one alternating nano-sheet channel layer, wherein the one of the two or more nano-sheet devices has a different threshold voltage, VT, than the other of the two or more nano-sheet devices by altering the length of the at least one alternating nano-sheet channel layer. ### Claim 15 (depends on 14) The method of claim 14, wherein an isotropic etch forms the indentations having a predetermined indentation depth in the range of about 2 nm to about 10 nm. ### Claim 16 (depends on 14) The method of claim 14, wherein the sacrificial release layers have a thickness in the range of about 5 nm to about 20 nm. ### Claim 17 (depends on 14) The method of claim 14, wherein the sacrificial release layers are silicon-germanium (SiGe). ### Claim 18 (depends on 14) The method of claim 14, wherein the at least one alternating nano-sheet channel layer is epitaxially grown on a crystalline surface of the substrate. ### Claim 19 (depends on 14) The method of claim 14, wherein the at least one alternating nano-sheet channel layer is a single crystal silicon layer on a crystalline sacrificial release layer.