# US 10,312,336 B2 · Memory transistor with multiple charge storing layers and a high work function gate electrode

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- Number: US 10,312,336 B2
- Document ID: US10312336B2
- Status: Granted
- Kind: B2
- Application number: 15/864,832
- Filed: 2018-01-08
- Published: 2018-06-07
- Granted: 2019-06-04
- Earliest claimed: 2007-05-25
- Assignees: Cypress Semiconductor Corporation
- Applicants: Cypress Semiconductor Corporation
- Inventors: Igor Polishchuk; Sagy Charel Levy; Krishnaswamy Ramkumar
- Web page: https://patentgrep.com/patent/US10312336B2

## CPC

- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10B 43/30: characterised by the memory core region
- H10B 43/40: characterised by the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide, and the first and the second dielectric layers include a nitride. Other embodiments are also disclosed.

## Claims

### Claim 1

A memory device, comprising:
a gate structure including a high work function gate electrode comprising a doped polysilicon layer;
a channel positioned between and electrically connecting a first diffusion region and a second diffusion region; and
a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel,
wherein the multi-layer charge trapping layer comprises a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers, and wherein the anti-tunneling layer comprises an oxide, and the first and the second dielectric layers both comprise oxynitride, wherein the oxynitride of the first and second dielectric layers have different stoichiometric compositions, and wherein the stoichiometric composition of the first dielectric layer results in it being substantially trap free, and the stoichiometric composition of the second dielectric layer results in it being trap dense.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the channel, first and second diffusion regions are formed at least partially within a semiconductor material structure.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein the channel, first and second diffusion regions are disposed above a semiconductor material structure.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the channel, first and second diffusion regions are suspended above a semiconductor material structure.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the first dielectric layer is disposed abutting the tunnel dielectric layer, and wherein the blocking dielectric layer is disposed abutting the second dielectric layer.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein the channel includes a silicon nanowire channel.

### Claim 7 (depends on 6)

The memory device of claim 6, further comprising a gate-all-around (GAA) structure wherein the silicon nanowire channel is enclosed on all four sides by the gate structure.

### Claim 8

A semiconductor device, comprising:
a memory transistor formed over a substrate, the memory transistor including:
a gate structure;
a channel positioned between and electrically connecting a first diffusion region formed in the substrate and a second diffusion region formed above the substrate, wherein the channel is vertical and formed in a cylinder of semiconducting material oriented substantially perpendicular to a surface of the substrate; and
a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel, wherein the multi-layer charge trapping layer comprises a first dielectric layer disposed abutting the tunnel dielectric layer, an anti-tunneling layer abutting the first dielectric layer, and a second dielectric layer abutting the anti-tunneling layer, and wherein the first and the second dielectric layers include a nitride, and the anti-tunneling layer is thinner than the first and second dielectric layers and comprises a stoichiometric composition substantially free of nitride; and
a metal oxide semiconductor (MOS) logic device formed at least partially over the surface of the substrate, MOS logic device including a gate oxide layer and a gate electrode disposed thereon.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first and second dielectric layers have different stoichiometry.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein a stoichiometric composition of the first dielectric layer results in it being substantially trap free, and a stoichiometric composition of the second dielectric layer results in it being trap dense.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the MOS logic device is formed at least partially within the substrate.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein the first dielectric layer of the multi-layer charge trapping layer is disposed abutting the tunnel dielectric layer, and wherein the blocking dielectric layer is disposed abutting the second dielectric layer.

### Claim 14

A semiconductor device, comprising:
a memory transistor including:
a gate structure including a high work function gate electrode comprising a doped polysilicon layer;
a channel positioned between and electrically connecting a first diffusion region and a second diffusion region; and
a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel, wherein the multi-layer charge trapping layer comprises a first dielectric layer disposed abutting the tunnel dielectric layer, an anti-tunneling layer abutting the first dielectric layer, and a second dielectric layer abutting the anti-tunneling layer, and wherein the anti-tunneling layer comprises a stoichiometric composition adapted to reduce a probability of electron charge in the second nitride layer from tunneling into the first nitride layer during programming of the memory transistor; and
a metal oxide semiconductor (MOS) logic device including a gate oxide layer and a gate electrode disposed thereon.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first and second dielectric layers have different stoichiometry.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein a stoichiometric composition of the first dielectric layer results in it being substantially trap free, and a stoichiometric composition of the second dielectric layer results in it being trap dense.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.