# US 10,312,332 B2 · Semiconductor device and method of forming the same

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- Number: US 10,312,332 B2
- Document ID: US10312332B2
- Status: Granted
- Kind: B2
- Application number: 15/489,841
- Filed: 2017-04-18
- Published: 2018-10-18
- Granted: 2019-06-04
- Earliest claimed: 2017-04-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon-Jhy Liaw
- Web page: https://patentgrep.com/patent/US10312332B2

## CPC

- H10D 64/01: Manufacture or treatment
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is provided, which includes a substrate, a gate and a gate contact. The substrate has a well region, which has a source, a drain and a channel region extending between the source and the drain. The gate is on the well region and extends across the channel region. The gate contact is directly on the gate and vertically overlaps with the channel region. The gate contact has a strip shape of which a ratio of a length to a width is at least 2. The gate contact includes a gate conductive plug and a gate contact dielectric. The gate conductive plug directly contacts the gate. The gate contact dielectric surrounds side surfaces of the gate conductive plug and has a frame shape. A dielectric constant of the gate contact dielectric is substantially greater than 4.9.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a well region, the well region having a source, a drain and a channel region laterally between the source and the drain, wherein a plurality of fins are disposed on the channel region;
a gate on the well region and laterally across the fins; and
a gate contact directly on the gate and vertically overlapping with at least one of the fins, the gate contact having a first strip shape of which a ratio of a length to a width is at least 2 and comprising:
a first conductive plug directly contacting the gate; and
a gate contact dielectric surrounding side surfaces of the first conductive plug and having a first frame shape, wherein a dielectric constant of the gate contact dielectric is greater than 4.9.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the gate contact dielectric is in a range from 5 angstroms to 50 angstroms.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a material of the gate contact dielectric is nitride-based dielectric, metal-oxide dielectric, hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), or combinations thereof.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
an inter-layer dielectric (ILD) layer on the gate and the substrate, the ILD layer defining an opening on the gate, the opening filled by the gate contact;
wherein the gate contact dielectric is conformal to sidewalls of the opening.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a dielectric constant of the ILD layer is less than 4.5.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a length of the gate contact extends in a first horizontal direction, and a length of each of the fins extends in a second horizontal direction perpendicular to the first horizontal direction.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a source/drain contact directly on the source or the drain, the source/drain contact comprising:
a second conductive plug directly contacting the source or the drain; and
a source/drain contact dielectric surrounding side surfaces of the second conductive plug and having a second frame shape, wherein a dielectric constant of the source/drain contact dielectric is greater than 4.9.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising:
a first metal line electrically coupled to the gate contact through a first via; and
a second metal line electrically coupled to the source/drain contact through a second via;
wherein the first metal line and the second metal line are parallel to each other and are in a same metal layer, and wherein the first via vertically overlaps with at least one of the fins.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the source/drain contact has a second strip shape of which a ratio of a length to a width is at least 2.

### Claim 10 (depends on 7)

The semiconductor device of claim 7, wherein a length of the gate contact and a length of the source/drain contact extend in a same horizontal direction.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein a material of the first conductive plug is titanium, titanium nitride (TiN), tantalum nitride (TaN), cobalt, ruthenium, platinum, tungsten, aluminum, copper, or combinations thereof.

### Claim 12

A semiconductor device, comprising:
a substrate having a well region, the well region having a source, a drain and a channel region laterally between the source and the drain, wherein a plurality of fins are disposed on the channel region;
a gate on the well region and laterally across the fins;
a gate contact directly on the gate and vertically overlapping with at least one of the fins, the gate contact having a first strip shape, wherein a ratio of a length of the first strip shape to a width of the first strip shape is at least 2, and the gate contact comprises:
a first conductive plug directly contacting the gate; and
a gate contact dielectric surrounding side surfaces of the first conductive plug and having a first frame shape, wherein a dielectric constant of the gate contact dielectric is greater than 4.9; and
a first metal line electrically coupled to the gate contact through a first via;
wherein a length of the gate contact extends in a first horizontal direction, and a length of the first metal line extends in a second horizontal direction that is perpendicular to the first horizontal direction.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a length of each of the fins extends in the second horizontal direction.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, further comprising:
a source/drain contact directly on the source or the drain, the source/drain contact comprising:
a second conductive plug directly contacting the source or the drain; and
a source/drain contact dielectric surrounding side surfaces of the second conductive plug and having a second frame shape, wherein a dielectric constant of the source/drain contact dielectric is greater than 4.9; and
a second metal line electrically coupled to the source/drain contact through a second via;
wherein a length of the source/drain contact extends in the first horizontal direction, and a length of the second metal line extends in the second horizontal direction.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the source/drain contact has a second strip shape, wherein a ratio of a length of the second strip shape to a width of the second strip shape is at least 2.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein a thickness of the gate contact dielectric is in a range from 5 angstroms to 50 angstroms.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, wherein a material of the gate contact dielectric is nitride-based dielectric, metal-oxide dielectric, hafnium oxide (HfO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), or combinations thereof.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, further comprising:
an inter-layer dielectric (ILD) layer on the gate and the substrate, the ILD layer defining an opening on the gate, the opening filled by the gate contact;
wherein the gate contact dielectric is conformal to sidewalls of the opening, and a dielectric constant of the ILD layer is less than 4.5.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein a material of the first conductive plug is titanium, titanium nitride (TiN), tantalum nitride (TaN), cobalt, ruthenium, platinum, tungsten, aluminum, copper, or combinations thereof.

### Claim 20

A semiconductor device, comprising:
a substrate having a well region, the well region having a source, a drain and a channel region laterally between the source and the drain, wherein a plurality of fins are disposed on the channel region;
a gate on the well region and laterally across the fins;
a gate contact directly on the gate and vertically overlapping with at least one of the fins, the gate contact having a strip shape, wherein a ratio of a length of the strip shape to a width of the strip shape is at least 2, and the gate contact comprises:
a first conductive plug directly contacting the gate; and
a gate contact dielectric surrounding side surfaces of the first conductive plug and having a first frame shape, wherein a dielectric constant of the gate contact dielectric is greater than 4.9;
a first metal line electrically coupled to the gate contact through a first via;
a source/drain contact directly on the source or the drain, the source/drain contact comprising:
a second conductive plug directly contacting the source or the drain; and
a source/drain contact dielectric surrounding side surfaces of the second conductive plug and having a second frame shape, wherein a dielectric constant of the source/drain contact dielectric is greater than 4.9; and
a second metal line electrically coupled to the source/drain contact through a second via;
wherein each of a length of the gate contact and a length of the source/drain region extends in a first horizontal direction, and each of a length of each of the fins, a length of the first metal line and a length of the second metal line extend in a second horizontal direction that is perpendicular to the first horizontal direction.