# US 10,312,329 B2 · Semiconductor device and manufacturing method therefor

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- Number: US 10,312,329 B2
- Document ID: US10312329B2
- Status: Granted
- Kind: B2
- Application number: 15/683,029
- Filed: 2017-08-22
- Published: 2018-04-05
- Granted: 2019-06-04
- Earliest claimed: 2016-09-30
- Assignees: Semiconductor Manufacturing International (Beijing) Corporation; Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Beijing) Corporation; Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Ming Zhou
- Web page: https://patentgrep.com/patent/US10312329B2

## CPC

- H10D 62/882: {Graphene}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/43: Layouts of interconnections
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to the technical field of semiconductor processes, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate structure including a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer includes a nanowire; forming a base layer on the substrate structure; selectively growing a graphene layer on the base layer; forming a second dielectric layer on the graphene layer; forming an electrode material layer on the substrate structure to cover the second dielectric layer; defining an active region; and forming a gate by etching at least a portion of a stack layer to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, where the gate structure includes a portion of the electrode material layer and the second dielectric layer. The present disclosure incorporates graphene into the semiconductor process and makes use of the features of graphene in a dual-gate structure.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
providing a substrate structure comprising a substrate and a first material layer on the substrate, wherein a recess is formed in the substrate and the first material layer comprises a nanowire spanning and suspended above the recess;
forming a base layer on the substrate structure, wherein the base layer comprises at least a first portion covering an exposed surface of the nanowire and a second portion covering an exposed surface of the recess;
selectively growing a graphene layer on the base layer;
forming a second dielectric layer on the graphene layer;
forming an electrode material layer on the substrate structure to cover the second dielectric layer;
partially removing the electrode material layer, the second dielectric layer, and the graphene layer so as to define an area of an active region wherein at least a portion of a stack layer of the electrode material layer, the second dielectric layer, and the graphene layer on the nanowire remains and is within the active region; and
forming a gate by etching at least a portion of the stack layer remaining within the active region to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, wherein the gate structure comprises a portion of the electrode material layer and the second dielectric layer.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
after defining the gate, removing portions of the graphene layer and the second dielectric layer which are on a surface of the recess.

### Claim 3 (depends on 1)

The method according to claim 1, wherein defining the active region comprises:
forming a patterned mask on the electrode material layer, the patterned mask shielding at least a portion of the nanowire; and
removing, by using the patterned mask, portions of the electrode material layer, the second dielectric layer, and the graphene layer not shielded by the patterned mask.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the patterned mask further shields at least a portion of the recess.

### Claim 5 (depends on 3)

The method according to claim 3, wherein
the first material layer further comprises a portion above the first dielectric layer at two ends of the recess bonded to the portion of the first material layer forming the nanowire; and
the patterned mask shields the nanowire, and further shields at least a portion of the first material layer that is bonded to the nanowire.

### Claim 6 (depends on 5)

The method according to claim 5 further comprising:
forming a fourth dielectric layer to cover at least the substrate structure and the area of the active region;
forming a hole through the fourth dielectric layer, the second dielectric layer, and the graphene layer to the at least a portion of the first material layer;
forming an insulating material layer on a side wall of the hole; and
filling the hole with a conductive material after forming the insulating material layer on the side wall of the hole so as to form a contact component to the at least a portion of the first material layer,
wherein the insulating material layer electrically isolates the graphene layer from the contact component.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
the substrate comprises a substrate layer and a first dielectric layer on the substrate layer;
the first material layer is on the first dielectric layer;
the recess is formed in the first dielectric layer; and
wherein providing a substrate structure comprises:
providing an initial substrate structure comprising the substrate and the first material layer on the first dielectric layer of the substrate;
patterning the first material layer to define a region covering the nanowire and two sides of the nanowire along the length direction of the nanowire; and
removing at least upper portions of the first dielectric layer of the defined region to form the recess.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the recess further extends through the first dielectric layer into the substrate layer.

### Claim 9 (depends on 1)

The method according to claim 1, wherein
the graphene layer comprises a first portion on a surface of the first portion of the base layer, and a second portion on a surface of the second portion of the base layer;
the second dielectric layer comprises a first portion on a surface of the first portion of the graphene layer, and a second portion on a surface of the second portion of the graphene layer; and
the electrode material layer is further formed to fill a space below the nanowire and between the first portion of the second dielectric layer and the second portion of the second dielectric layer when forming the electrode material layer.

### Claim 10 (depends on 1)

The method according to claim 1, wherein:
the first material layer comprises polysilicon, doped polysilicon, or silicon germanium;
the base layer comprises an oxide of aluminum;
the first dielectric layer comprises an oxide of silicon; and
the second dielectric layer comprises boron nitride, an oxide of silicon, an oxide of hafnium, an oxide of aluminum, or a nitride of aluminum.

### Claim 11 (depends on 1)

The method according to claim 1, wherein
the base layer comprises an oxide of aluminum; and
selectively growing the graphene layer on the base layer comprises selectively growing the graphene layer at a temperature of 900-1000° C. by a chemical vapor deposition process using methane and hydrogen.

### Claim 12 (depends on 1)

The method according to claim 1, wherein
the nanowire comprises doped polysilicon; and
the portion of the electrode material layer in the gate structure is used as a first gate, and the nanowire is used as a second gate.

### Claim 13 (depends on 1)

The method according to claim 1, wherein defining the gate comprises:
forming a third dielectric layer to cover at least the substrate structure and the area of the active region; and
etching, by using a patterned mask defining a gate area, a portion of the third dielectric layer outside the gate area and at least a portion of the stack layer within the active region but outside the gate area to at least the second dielectric layer so as to form a gate structure surrounding an intermediate portion of the nanowire, wherein the gate structure comprises a portion of the electrode material layer and the second dielectric layer.

### Claim 14 (depends on 1)

The method according to claim 1, after the forming the gate, further comprising:
forming a fourth dielectric layer to cover at least the substrate structure and the area of the active region;
forming a hole through the fourth dielectric layer and the second dielectric layer to the graphene layer, the hole being separated from the gate structure; and
filling the hole with a conductive material, so as to form a contact component to the graphene layer.

### Claim 15 (depends on 1)

The method according to claim 1, further comprising:
forming a fourth dielectric layer to cover at least the substrate structure and the area of the active region;
forming a hole through the fourth dielectric layer, the second dielectric layer, and the graphene layer to the first material layer;
forming an insulating material layer on a side wall of the hole; and
filling the hole with a conductive material after forming the insulating material layer on the side wall of the hole so as to form a contact component to the first material layer.