# US 10,312,327 B2 · FinFETs having dielectric punch-through stoppers

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- Number: US 10,312,327 B2
- Document ID: US10312327B2
- Status: Granted
- Kind: B2
- Application number: 15/665,184
- Filed: 2017-07-31
- Published: 2017-11-16
- Granted: 2019-06-04
- Earliest claimed: 2008-05-06
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Hung Chang; Chen-Hua Yu; Chen-Nan Yeh
- Web page: https://patentgrep.com/patent/US10312327B2

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having a topmost surface;
a planar transistor on the topmost surface of the semiconductor substrate; and
a FinFET on the semiconductor substrate, the FinFET comprising:
a semiconductor fin having a topmost surface that is substantially level with the topmost surface of the semiconductor substrate; and
a first isolation structure extending between the semiconductor fin and the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor fin has a first sidewall and a second sidewall opposite the first sidewall, and wherein the first isolation structure extends from the first sidewall to the second sidewall.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first isolation structure comprises silicon oxide.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the semiconductor fin is made of a first semiconductor material, and wherein first isolation structure comprises an oxide of the first semiconductor material.

### Claim 5 (depends on 1)

The semiconductor device of claim 1 wherein the semiconductor fin has a first sidewall and a second sidewall opposite the first sidewall, and wherein the first isolation structure extends laterally beyond the first sidewall and the second sidewall.

### Claim 6 (depends on 1)

The semiconductor device of claim 1 wherein the planar transistor is disposed on a mesa of the semiconductor substrate, and wherein a second isolation structure extends into the mesa of the semiconductor substrate.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the mesa is made of a second semiconductor material, and wherein the second isolation structure comprises an oxide of the second semiconductor material.

### Claim 8 (depends on 7)

The semiconductor device of claim 7 further comprising a shallow trench isolation oxide extending from the first isolation structure to the second isolation structure.

### Claim 9 (depends on 8)

The semiconductor device of claim 8 further comprising a stressor region surrounding the planar transistor and interjacent a portion of the mesa above the second isolation structure and the shallow trench isolation oxide.

### Claim 10 (depends on 9)

The semiconductor device of claim 9 further comprising an oxide liner extending along a sidewall of the mesa above the second isolation structure, wherein the oxide liner is disposed between the stressor region and the mesa.

### Claim 11

A semiconductor device comprising:
a semiconductor substrate;
a planar transistor comprising a source/drain region disposed in a topmost surface of the semiconductor substrate;
a fin having a topmost surface substantially level with the topmost surface of the semiconductor substrate and extending below the topmost surface of the semiconductor substrate, the fin including an upper portion and a lower portion;
a first isolation structure interjacent the upper portion of the fin and the lower portion of the fin; and
a first gate structure over and extending along sidewalls of the fin.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the first isolation structure is an oxide of a semiconductor material of the fin.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the first isolation structure extends directly under the upper portion of the fin.

### Claim 14 (depends on 11)

The semiconductor device of claim 11 further comprising a second fin having a topmost surface substantially level with the topmost surface of the semiconductor substrate and extending below the topmost surface of the semiconductor substrate, the second fin including a second upper portion and a second lower portion and a second isolation structure interjacent the second upper portion and the second lower portion, the second isolation structure being at a distance below the topmost surface of the semiconductor substrate that is greater than the distance below the topmost surface of the semiconductor substrate for the first isolation structure.

### Claim 15 (depends on 11)

The semiconductor device of claim 11 further comprising a third isolation structure extending directly under a second gate structure of the planar transistor.

### Claim 16 (depends on 11)

The semiconductor device of claim 11 further comprising a stressor region encircling a portion of the semiconductor substrate disposed directly under a second gate structure of the planar transistor.

### Claim 17

A semiconductor device comprising:
a semiconductor substrate having a topmost surface;
a planar transistor on the topmost surface of the semiconductor substrate; and
a FinFET on the semiconductor substrate, the FinFET comprising:
a semiconductor fin having a topmost surface that is substantially level with the topmost surface of the semiconductor substrate; and
a first isolation structure extending between the semiconductor fin and the semiconductor substrate, wherein the semiconductor fin has a first sidewall and a second sidewall opposite the first sidewall, and wherein the first isolation structure extends from the first sidewall to the second sidewall.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first isolation structure comprises silicon oxide.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the semiconductor fin is made of a first semiconductor material, and wherein first isolation structure comprises an oxide of the first semiconductor material.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, wherein the first isolation structure extends laterally beyond the first sidewall and the second sidewall.