# US 10,312,326 B1 · Long channels for transistors

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- Number: US 10,312,326 B1
- Document ID: US10312326B1
- Status: Granted
- Kind: B1
- Application number: 15/844,923
- Filed: 2017-12-18
- Published: 2019-06-20
- Granted: 2019-06-04
- Earliest claimed: 2017-12-18
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Robin Hsin Kuo Chao; Choonghyun Lee; Heng Wu; Chun Wing Yeung; Jingyun Zhang
- Web page: https://patentgrep.com/patent/US10312326B1

## CPC

- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 30/01: Manufacture or treatment
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/0116: {to Group III-V semiconductors}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

## Claims

### Claim 1

A method for fabricating a semiconductor device, the method comprising:
forming a gate on a first fin, a second fin, and a third fin arranged on a substrate;
depositing a semiconductor material on the first fin, the second fin, and the third fin;
depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin;
forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin; and
depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

### Claim 2 (depends on 1)

The method of claim 1, wherein a pitch between the first fin and the second fin comprises at least 30 nanometers (nm).

### Claim 3 (depends on 1)

The method of claim 1, wherein depositing the semiconductor material comprises applying an epitaxial growth process.

### Claim 4 (depends on 1)

The method of claim 1, wherein subsequent to depositing the metal a channel is formed that crosses through the gate in three areas.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first trench extends through the ILD to the semiconductor material on the first fin.

### Claim 6 (depends on 5)

The method of claim 5, wherein the second trench extends through the ILD to the semiconductor material on the second fin and the third fin.

### Claim 7 (depends on 1)

The method of claim 1, wherein the third trench extends through the ILD to the semiconductor material on the first fin and the second fin, and the fourth trench extends through the ILD to the semiconductor material on the third fin.

### Claim 8

A method for fabricating a semiconductor device, the method comprising:
forming a gate on a first fin, a second fin, and a third fin arranged on a substrate;
removing a portion of the third fin to decrease a height of the third fin;
depositing a semiconductor material on the first fin, the second fin, and the third fin;
depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin;
forming a first trench through the ILD on a first side of the gate, and a second trench through the ILD on a second side of the gate, the first trench exposing the semiconductor material on the first fin and the second trench exposing the semiconductor material on the third fin; and
depositing a metal in the first trench and the second trench.

### Claim 9 (depends on 8)

The method of claim 8, wherein a pitch of the first fin and the second fin comprises less than 30 nanometers (nm).

### Claim 10 (depends on 8)

The method of claim 8, wherein depositing the semiconductor material comprises an epitaxial growth process.

### Claim 11 (depends on 10)

The method of claim 10, wherein the semiconductor material deposited on the first fin and the second fin overlaps one another.

### Claim 12 (depends on 8)

The method of claim 8, wherein after depositing the metal, a channel is formed that crosses through the gate in three areas.

### Claim 13 (depends on 8)

The method of claim 8, wherein the gate comprises a sacrificial gate material.

### Claim 14 (depends on 13)

The method of claim 13, wherein the gate is replaced with a metal gate stack before forming the first trench on the first side of the gate and the second trench on the second side of the gate.