# US 10,312,323 B2 · Bulk nanosheet with dielectric isolation

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- Number: US 10,312,323 B2
- Document ID: US10312323B2
- Status: Granted
- Kind: B2
- Application number: 15/651,420
- Filed: 2017-07-17
- Published: 2017-11-02
- Granted: 2019-06-04
- Earliest claimed: 2015-10-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Junli Wang
- Web page: https://patentgrep.com/patent/US10312323B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/364: {of IGFETs}
- H10D 62/834: further characterised by the dopants
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/0125: {comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

## Claims

### Claim 1

A nanowire field effect transistor (FET) device, comprising:
a bulk semiconductor wafer comprising a dielectric isolation region in a top portion thereof, wherein the dielectric isolation region comprises a thermal oxide;
nanowire stacks on the bulk semiconductor wafer, wherein each of the nanowire stacks comprises alternating layers of a sacrificial material and a channel material, wherein portions of the channel material are released from the nanowire stacks in a channel region of the FET device and comprise nanowire channels of the FET device, and wherein a first layer in the nanowire stacks comprises the sacrificial material and is present on the bulk semiconductor wafer; and
a gate surrounding the nanowire channels in the channel region of the device, wherein the first layer in the nanowire stacks has an inverted triangular shape beneath the gate in the channel region of the device.

### Claim 2 (depends on 1)

The nanowire FET device of claim 1, wherein the gate completely surrounds one or more of the nanowire channels in a gate-all-around configuration.

### Claim 3 (depends on 1)

The nanowire FET device of claim 1, further comprising:
at least one dopant implanted into the top portion of the bulk semiconductor wafer.

### Claim 4 (depends on 3)

The nanowire FET device of claim 3, wherein the at least one dopant is selected from the group consisting of: fluorine, phosphorous, and combinations thereof.

### Claim 5 (depends on 3)

The nanowire FET device of claim 3, wherein the at least one dopant is implanted into the top portion of the bulk semiconductor wafer at a dose of from about from about 5×1015 atoms/cm2 to about 5×1016 atoms/cm2, and ranges therebetween.

### Claim 6 (depends on 3)

The nanowire FET device of claim 3, wherein the bulk semiconductor wafer has a thickness of from about 0.1 millimeters to about 0.75 millimeters, and ranges therebetween.

### Claim 7 (depends on 3)

The nanowire FET device of claim 3, wherein the top portion of the bulk semiconductor wafer comprises a first thickness of from about 100 angstroms to about 500 angstroms, and ranges therebetween, of the bulk semiconductor wafer.

### Claim 8 (depends on 1)

The nanowire FET device of claim 1, wherein the sacrificial material comprises silicon germanium and the channel material comprises silicon.

### Claim 9 (depends on 1)

The nanowire FET device of claim 1, wherein the sacrificial material comprises silicon and the channel material comprises silicon germanium.

### Claim 10 (depends on 1)

The nanowire FET device of claim 1, wherein the first layer in the nanowire stacks present on the bulk semiconductor wafer is thicker than other layers in the nanowire stacks.

### Claim 11 (depends on 10)

The nanowire FET device of claim 10, wherein the first layer in the nanowire stacks has a thickness of from about 20 nanometers to about 35 nanometers, and ranges therebetween.

### Claim 12 (depends on 10)

The nanowire FET device of claim 10, wherein the other layers in the nanowire stacks have a thickness of from about 10 nanometers to about 25 nanometers, and ranges therebetween.

### Claim 13 (depends on 1)

The nanowire FET device of claim 1, further comprising:
spacers on opposite sides of the gate.

### Claim 14 (depends on 13)

The nanowire FET device of claim 13, wherein the spacers offset the gate from source and drain regions of the device which comprise portions of the nanowire stacks extending out from the gate.

### Claim 15 (depends on 14)

The nanowire FET device of claim 14, wherein the source and drain regions of the device comprise an in-situ doped epitaxial material selected from the group consisting of: silicon, silicon carbide, and silicon germanium.

### Claim 16 (depends on 1)

The nanowire FET device of claim 1, wherein the gate is a metal gate.

### Claim 17 (depends on 1)

The nanowire FET device of claim 1, further comprising:
a gate dielectric separating the gate from the nanowire channels, wherein the gate dielectric is selected from the group consisting of: hafnium oxide and lanthanum oxide.

### Claim 18 (depends on 1)

The nanowire FET device of claim 1, wherein the bulk semiconductor wafer comprises a material selected from the group consisting of: silicon, strained silicon, silicon carbide, germanium, silicon germanium, silicon-germanium-carbon, a silicon alloy, a germanium alloy, gallium arsenide, indium arsenide, indium phosphide, and combinations thereof.

### Claim 19 (depends on 1)

The nanowire FET device of claim 1, wherein the dielectric isolation region is continuous along the top portion of the bulk semiconductor wafer beneath the nanowire stacks.