# US 10,312,321 B2 · Trigate device with full silicided epi-less source/drain for high density access transistor applications

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- Number: US 10,312,321 B2
- Document ID: US10312321B2
- Status: Granted
- Kind: B2
- Application number: 14/839,213
- Filed: 2015-08-28
- Published: 2017-03-02
- Granted: 2019-06-04
- Earliest claimed: 2015-08-28
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Michael A. Guillorn; Fei Liu; Zhen Zhang
- Web page: https://patentgrep.com/patent/US10312321B2

## CPC

- H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers}
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 1/00: Resistors, capacitors or inductors
- H10D 1/68: Capacitors having no potential barriers
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/40: of conductive or resistive materials
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 50/264: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 20/0698: {Local interconnections}
- H10W 20/43: Layouts of interconnections
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.

## Claims

### Claim 1

A semiconductor structure comprising:
a deep trench capacitor embedded in a substrate;
a conductive strap structure in contact with, and overlying, an entirety of a topmost surface of an inner electrode of the deep trench capacitor;
a doped metal semiconductor alloy conductive strap structure located on a topmost surface of the conductive strap structure; and
an access transistor comprising:
a semiconductor fin located on the substrate and laterally adjacent to the doped metal semiconductor alloy conductive strap structure,
a gate stack overlying a body region of the semiconductor fin,
source/drain regions located in portions of the semiconductor fin and laterally surrounding the body region, wherein an entirety of each of the source/drain regions is alloyed with a metal, and
a segregated interfacial dopant layer located at an interface between each of the source/drain regions and the body region, wherein the doped metal semiconductor alloy conductive strap structure, the source/drain regions, the segregated interfacial dopant layer and the body region of the semiconductor fin have topmost surfaces that are coplanar with each other.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the doped metal semiconductor alloy conductive strap structure laterally contacts one of the source/drain regions.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the gate stack comprises a gate dielectric, a gate electrode, and a gate cap.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, where the deep trench capacitor further comprises a node dielectric, and an outer electrode.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the node dielectric comprises silicon nitride or a dielectric metal oxide.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, further comprising a first gate spacer present on each sidewall of the gate stack, the first gate spacer vertically contacting a portion of each of the source/drain regions.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, further comprising a second gate spacer present on the first gate spacer, the second gate spacer vertically contacting another portion of each of the source/drain regions.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein each of the first gate spacer and the second gate spacer comprises silicon nitride, silicon boron carbon nitride or silicon carbon oxynitride.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein each of the source/drain regions and the doped metal semiconductor alloy conductive strap structure comprises a metal silicide or a metal germicide.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the segregated interfacial dopant layer has a greater dopant concentration than a dopant concentration of each of the source/drain regions.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the gate stack contacts a top surface and sidewalls of the body region.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein the substrate comprises a handle substrate and a buried insulator layer located on the handle substrate, wherein the topmost surface of the deep trench capacitor is located between a top surface of the buried insulator layer and a bottom surface of the buried insulator layer.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the conductive strap structure is composed of a conductive material.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, wherein a p-n junction is formed between an outer electrode of the deep trench capacitor and the handle substrate.

### Claim 15 (depends on 1)

The semiconductor structure of claim 1, wherein the inner electrode comprises a doped semiconductor material.

### Claim 16

A semiconductor structure comprising:
a deep trench capacitor embedded in a substrate;
a conductive strap structure in contact with, and overlying, an entirety of a topmost surface of an inner electrode of the deep trench capacitor, wherein the conductive strap structure comprises, from bottom to top, a base portion composed of a conductive material, and a fin portion composed of a doped metal semiconductor alloy; and
an access transistor comprising:
a semiconductor fin located on the substrate and laterally adjacent to the fin portion of the conductive strap structure,
a gate stack overlying a body region of the semiconductor fin,
source/drain regions located in portions of the semiconductor fin and laterally surrounding the body region, wherein an entirety of each of the source/drain regions is alloyed with a metal, and
a segregated interfacial dopant layer located at an interface between each of the source/drain regions and the body region, wherein the fin portion of the conductive strap structure, the source/drain regions, the segregated interfacial dopant layer and the body region of the semiconductor fin have topmost surfaces that are coplanar with each other.