# US 10,312,311 B2 · Thin film transistor, fabrication method thereof, array substrate, and display device

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- Number: US 10,312,311 B2
- Document ID: US10312311B2
- Status: Granted
- Kind: B2
- Application number: 15/519,313
- Filed: 2016-11-08
- Published: 2018-05-17
- Granted: 2019-06-04
- Earliest claimed: 2016-03-11
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd
- Inventors: Zheng Liu; Xiaolong Li; Lujiang Huang Fu
- Web page: https://patentgrep.com/patent/US10312311B2

## CPC

- H10K 59/1213: {the pixel elements being TFTs}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6725: {having supplementary regions or layers for improving the flatness of the device}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 50/283: {by chemical means}
- H10P 50/287: {by chemical means}
- G02F 1/13685: {Top gates}
- G02F 2202/104: poly-Si
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10K 59/1201: {Manufacture or treatment}
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The disclosed subject matter provides a thin film transistor and a fabricating method thereof. The thin film transistor includes a substrate, a source electrode and a drain electrode on the substrate, an active layer on the source and drain electrodes, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer. The active layer extends from the source electrode towards the drain electrode along a non-linear path.

## Claims

### Claim 1

A thin film transistor, comprising:
a substrate;
a source electrode and a drain electrode on the substrate;
an active layer on the source electrode and the drain electrode, the active layer extending from the source electrode towards the drain electrode along a non-linear path; and
an intermediate insulating layer, a portion of the intermediate insulating layer being arranged on the source electrode and the drain electrode and forming a raised profile layer from the substrate;
wherein:
the non-linear path of the active layer includes a first portion and a second portion connecting the first portion, the second portion extending in a direction away from the substrate and along the raised profile of the portion of the intermediate insulating layer, and
the active layer along the first portion of the non-linear path contacts the source and drain electrodes, and the active layer along the second portion of the non-linear path contacts the intermediate insulating layer.

### Claim 2 (depends on 1)

The thin film transistor of claim 1, further comprising:
a gate insulating layer on the active layer; and
a gate electrode on the gate insulating layer,
wherein the intermediate insulating layer is on one side of the active layer facing toward the substrate, and includes a hollowed region that corresponds to a region between the source electrode and the drain electrode.

### Claim 3 (depends on 2)

The thin film transistor of claim 2, wherein:
the source electrode and the drain electrode are on one side of the active layer facing toward the substrate; and
the gate insulating layer and the gate electrode are on another side of the active layer facing away from the substrate.

### Claim 4 (depends on 2)

The thin film transistor of claim 2, wherein:
the intermediate insulating layer is made of inorganic materials; and
a thickness of the intermediate insulating layer is between 2000 Å and 8000 Å.

### Claim 5 (depends on 2)

The thin film transistor of claim 2, wherein:
the intermediate insulating layer is made of organic materials; and
a thickness of the intermediate insulating layer is between 10000 Å and 20000 Å.

### Claim 6 (depends on 2)

The thin film transistor of claim 2, wherein:
the intermediate insulating layer has a multi-layer structure formed by stacking organic materials and inorganic materials; and
a thickness of the intermediate insulating layer is between 2000 Å and 20000 Å.

### Claim 7 (depends on 2)

The thin film transistor of claim 2, wherein:
slope angles of the intermediate insulating layer in the hollowed region are between 30° and 60°.

### Claim 8 (depends on 1)

The thin film transistor of claim 1, wherein:
the active layer has an approximate M shape.

### Claim 9 (depends on 2)

The thin film transistor of claim 2, wherein:
the gate electrode has an approximate V shape or an approximate U shape.

### Claim 10 (depends on 1)

An array substrate, comprising:
the thin film transistor of claim 1; and
a first electrode electrically connected to the drain electrode of the thin film transistor.

### Claim 11 (depends on 10)

The array substrate of claim 10, wherein the first electrode is a pixel electrode.

### Claim 12 (depends on 10)

The array substrate of claim 10, further comprising:
a top electrode; and
an organic material layer between the top electrode and the first electrode.

### Claim 13 (depends on 10)

A display device, comprising the array substrate of claim 10.

### Claim 14

A method for fabricating a thin film transistor, comprising:
providing a substrate;
forming a source electrode and a drain electrode on the substrate;
forming an intermediate insulating layer, a portion of the intermediate insulating layer being arranged on the source electrode and the drain electrode and forming a raised profile away from the substrate;
forming a polysilicon layer between the source electrode and the drain electrode;
forming a gate insulating layer on the polysilicon layer;
forming a gate electrode on the gate insulating layer; and
using the gate electrode as a mask, implanting ions into the polysilicon layer to form an active layer including a source region, a drain electrode region, and a channel region that is not subject to the ion implantation;
wherein:
the active layer extends from the source electrode towards the drain electrode along a non-linear path,
the non-linear path of the active layer includes a first portion and a second portion connecting the first portion, the second portion extending towards the gate electrode and along the raised profile of the intermediate insulating layer, and
the active layer along the first portion of the non-linear path contacts the source and drain electrodes, and the active layer along the second portion of the non-linear path contacts the intermediate insulating layer.

### Claim 15 (depends on 14)

The fabrication method of claim 14, further comprising:
etching a portion of the intermediate insulating layer to form a hollowed region between the source electrode and the drain electrode.

### Claim 16 (depends on 15)

The fabrication method of claim 15, wherein:
the intermediate insulating layer is made of inorganic materials; and
a thickness of the intermediate insulating layer is between 2000 Å and 8000 Å.

### Claim 17 (depends on 15)

The fabrication method of claim 15, wherein:
the intermediate insulating layer is made of organic materials; and
a thickness of the intermediate insulating layer is between 10000 Å and 20000 Å.

### Claim 18 (depends on 15)

The fabrication method of claim 15, wherein:
the intermediate insulating layer is made by stacking organic materials and inorganic materials to form a multi-layer structure; and
a thickness of the intermediate insulating layer is between 2000 Å and 20000 Å.

### Claim 19 (depends on 15)

The fabrication method of claim 15, wherein:
slope angles of the intermediate insulating layer in the hollowed region are between 30° and 60°.

### Claim 20 (depends on 15)

The fabrication method of claim 15, wherein:
the active layer is formed in an M shape; and
the gate electrode if formed in a V shape or a U shape.