# US 10,312,289 B1 · Semiconductor memory device

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- Number: US 10,312,289 B1
- Document ID: US10312289B1
- Status: Granted
- Kind: B1
- Application number: 16/040,671
- Filed: 2018-07-20
- Granted: 2019-06-04
- Earliest claimed: 2018-03-19
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Kensuke Ota; Masumi Saitoh
- Web page: https://patentgrep.com/patent/US10312289B1

## CPC

- H10B 63/34: {of the vertical channel field-effect transistor type}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/845: {the switching components being connected to a common vertical conductor}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8416: {adapted for supplying ionic species}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10W 20/43: Layouts of interconnections
- G11C 13/003: {Cell access}
- G11C 2013/005: {Read using potential difference applied between cell electrodes}
- G11C 2013/009: {Write using potential difference applied between cell electrodes}
- G11C 2213/15: Current-voltage curve
- G11C 2213/32: Material having simple binary metal oxide structure
- G11C 2213/52: Structure characterized by the electrode material, shape, etc.
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C 2213/79: Array wherein the access device being a transistor
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/823: {adapted for essentially horizontal current flow, e.g. bridge type devices}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device comprises a substrate, a plurality of first wirings arranged in a first direction crossing a surface of the substrate, a second wiring extending in the first direction, a variable resistance film provided between the first wiring and the second wiring, a third wiring extending in a second direction crossing the first direction, a select transistor provided between an end of the second wiring and the third wiring. In addition, the semiconductor memory device comprises a chalcogen layer provided at at least a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor.

## Claims

### Claim 1

A semiconductor memory device comprising:
a substrate;
a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
a second wiring extending in the first direction;
a variable resistance film provided between the first wiring and the second wiring;
a third wiring extending in a second direction crossing the first direction;
a select transistor provided between an end of the second wiring and the third wiring; and
a chalcogen layer provided at at least one of a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor, wherein
the select transistor comprises:
a semiconductor layer being connected to the second wiring or the third wiring, and including:
a first semiconductor region;
a second semiconductor region between the first semiconductor region and the chalcogen layer; and
a third semiconductor region between the first and second semiconductor regions; and
a gate electrode facing the third semiconductor region.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein
the first and second semiconductor regions include impurities of a first conductivity type,
the third semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

### Claim 3

A semiconductor memory device comprising:
a substrate;
a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
a second wiring extending in the first direction;
a variable resistance film provided between the first wiring and the second wiring;
a third wiring extending in a second direction crossing the first direction;
a select transistor provided between an end of the second wiring and the third wiring; and
a chalcogen layer provided at at least one of a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor, wherein
the select transistor comprises:
a semiconductor layer being connected to the second wiring or the third wiring, and including:
a first semiconductor region; and
a second semiconductor region between the first semiconductor region and the chalcogen layer; and
a gate electrode facing the second semiconductor region, and
the chalcogen layer is connected to the second semiconductor region.

### Claim 4 (depends on 3)

The semiconductor memory device according to claim 3, wherein
the first semiconductor region includes impurities of a first conductivity type,
the second semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

### Claim 5

A semiconductor memory device comprising:
a substrate;
a plurality of first wirings arranged in a first direction crossing a surface of the substrate;
a second wiring extending in the first direction;
a variable resistance film provided between the first wiring and the second wiring;
a third wiring extending in a second direction crossing the first direction;
a select transistor connected to the third wiring; and
a chalcogen layer connected to the select transistor and the second wiring, wherein
the select transistor comprises:
a semiconductor layer including one end connected to the third wiring, and, the other end connected to the chalcogen layer; and
a gate electrode facing the semiconductor layer in the second direction.

### Claim 6 (depends on 5)

The semiconductor memory device according to claim 5, wherein
the semiconductor layer comprises:
a first semiconductor region;
a second semiconductor region between the first semiconductor region and the chalcogen layer; and
a third semiconductor region between the first and second semiconductor regions, and
the gate electrode faces the third semiconductor region.

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein
the first and second semiconductor regions include impurities of a first conductivity type,
the third semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.

### Claim 8 (depends on 5)

The semiconductor memory device according to claim 5, wherein
the semiconductor layer comprises:
a first semiconductor region; and
a second semiconductor region between the first semiconductor region and the chalcogen layer,
the gate electrode faces the second semiconductor region, and
the chalcogen layer is connected to the second semiconductor region.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, wherein
the first semiconductor region includes impurities of a first conductivity type,
the second semiconductor region includes impurities of a second conductivity type, and
the second conductivity type differs from the first conductivity type.