# US 10,312,271 B2 · Array substrate, manufacturing method thereof and display device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,271 B2
- Document ID: US10312271B2
- Status: Granted
- Kind: B2
- Application number: 15/759,498
- Filed: 2017-08-07
- Published: 2019-05-02
- Granted: 2019-06-04
- Earliest claimed: 2016-09-23
- Assignees: Boe Technology Group Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.
- Inventors: Zheng Liu; Xiaolong Li
- Web page: https://patentgrep.com/patent/US10312271B2

## CPC

- G02F 1/133385: {with cooling means, e.g. fans}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6723: {having light shields}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/0227: {using structural arrangements to control crystal growth, e.g. placement of grain filters}
- H10D 86/0229: {characterised by control of the annealing or irradiation parameters}
- H10D 86/0251: {characterised by increasing the uniformity of device parameters}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/126: Shielding, e.g. light-blocking means over the TFTs
- H10K 59/8794: {Arrangements for heating and cooling}
- G02F 1/13685: {Top gates}
- H10D 86/021: {of multiple TFTs}
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

An array substrate, a manufacturing method thereof and a display device. The array substrate includes a substrate, a thin film transistor on the substrate, and including an active layer including a source region, a drain region and a channel region between the source region and the drain region; a heat dissipation layer disposed between the substrate and the drain region; and the orthographic projection of the heat dissipation layer on the substrate at least covers the orthographic projection of a part of the source region and a part of the drain region on the substrate. The manufacturing method is for the manufacturing of the array substrate. The array substrate can improve the sizes and uniformity of the crystal particles.

## Claims

### Claim 1

An array substrate, comprising:
a substrate;
a thin film transistor on the substrate, and comprising an active layer comprising a source region, a drain region, and a channel region between the source region and the drain region; and
a heat dissipation layer between the substrate and the active layer;
wherein
an orthographic projection of the heat dissipation layer on the substrate at least covers the orthographic projection of a part of the source region and a part of the drain region on the substrate, the heat dissipation layer is configured to make heat dissipation rates of the source region and the drain region larger than a heat dissipation rate of the channel region.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein the orthogonal projection of the heat dissipation layer on the substrate completely covers the orthogonal projection of the channel region.

### Claim 3 (depends on 1)

The array substrate according to claim 1, wherein the heat dissipation layer is a metal light-shielding layer.

### Claim 4 (depends on 1)

The array substrate according to claim 1, wherein the orthogonal projection of the heat dissipation layer on the substrate completely covers the orthogonal projection of the active layer on the substrate.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein the heat dissipation layer comprises a first portion corresponding to the channel region, a second portion corresponding to the source region, and a third portion corresponding to the drain region;
the size of the second portion beyond the source region is greater than the size of the first portion beyond the channel region, and the size of the third portion beyond the drain region is greater than the size of the first portion beyond the channel region, along the direction perpendicular to the length of the channel region.

### Claim 6 (depends on 5)

The array substrate according to claim 5, wherein the second portion extends beyond the source region and the third portion extends beyond the drain region along the direction of the length of the channel region.

### Claim 7 (depends on 5)

The array substrate according to claim 5, wherein the orthographic projection of the first portion on the substrate is larger than the orthographic projection of the channel region on the substrate, the orthographic projection of the second portion on the substrate is larger than the orthographic projection of the source region on the substrate, and the orthographic projection of the third portion on the substrate is larger than the orthographic projection of the drain region on the substrate.

### Claim 8 (depends on 4)

The array substrate according to claim 4, wherein the heat dissipation layer comprises a first portion corresponding to the channel region, a second portion corresponding to the source region, and a third portion corresponding to the drain region;
the area of the second portion beyond the source region is greater than the area of the first portion beyond the channel region; the area of the third portion beyond the drain region is greater than the area of the first portion beyond the channel region.

### Claim 9 (depends on 1)

The array substrate according to claim 1, wherein the heat dissipation layer comprises a first portion corresponding to the channel region, a second portion corresponding to the source region, and a third portion corresponding to the drain region;
areas of the second portion and the third portion are both greater than the area of the first portion.

### Claim 10 (depends on 1)

The array substrate according to claim 1, wherein a thermal conductivity of the heat dissipation layer is greater than 85 W/(m·K).

### Claim 11 (depends on 1)

The array substrate according to claim 1, wherein a thickness of the heat dissipation layer is 40˜200 nm.

### Claim 12 (depends on 1)

The array substrate according to claim 1, further comprising a buffer layer disposed between the heat dissipation layer and the active layer.

### Claim 13 (depends on 1)

A display device, comprising the array substrate according to claim 1.

### Claim 14

A manufacturing method of an array substrate, comprising:
forming a heat dissipation layer on a substrate;
forming an amorphous silicon layer on the heat dissipation layer;
processing the amorphous silicon layer to form an active layer comprising a source region, a drain region, and a channel region between the source region and the drain region,
wherein the orthographic projection of the heat dissipation layer on the substrate at least covers the orthographic projection of a part of the source region and a part of the drain region on the substrate, the heat dissipation layer is configured to make heat dissipation rates of the source region and the drain region larger than a heat dissipation rate of the channel region.

### Claim 15 (depends on 14)

The manufacturing method according to claim 14, wherein processing the amorphous silicon layer to form an active layer comprising a source region, a drain region, and a channel region between the source region and the drain region, comprising:
annealing the amorphous silicon layer to form a poly-silicon layer;
patterning the poly-silicon layer to form the active layer comprising the source region, the drain region, and the channel region between the source region and the drain region.

### Claim 16 (depends on 14)

The manufacturing method according to claim 14, wherein the heat dissipation layer is a metal light-shielding layer.

### Claim 17 (depends on 14)

The manufacturing method according to claim 14, wherein the orthogonal projection of the heat dissipation layer on the substrate completely covers the orthogonal projection of the active layer on the substrate.

### Claim 18 (depends on 17)

The manufacturing method according to claim 17, wherein the heat dissipation layer comprises a first portion corresponding to the channel region, a second portion corresponding to the source region, and a third portion corresponding to the drain region;
the size of the second portion beyond the source region is greater than the size of the first portion beyond the channel region, and the size of the third portion extends beyond the drain region is greater than the size of the first portion beyond the channel region, along the direction perpendicular to the length of the channel region.

### Claim 19 (depends on 14)

The manufacturing method according to claim 14, further comprising:
forming a gate insulating layer and a gate electrode on the active layer sequentially;
using the gate electrode as a mask, and performing ion-implanting on the active layer that is not blocked by the gate electrode;
forming an interlayer insulating layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are in contact with the active layer.

### Claim 20 (depends on 14)

The manufacturing method according to claim 14, further comprising: forming a buffer layer on the heat dissipation layer before forming the amorphous silicon layer.