# US 10,312,267 B2 · Semiconductor device and electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,267 B2 - Document ID: US10312267B2 - Status: Granted - Kind: B2 - Application number: 16/004,882 - Filed: 2018-06-11 - Published: 2018-12-13 - Granted: 2019-06-04 - Earliest claimed: 2009-12-11 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Hajime Kimura; Atsushi Umezaki; Shunpei Yamazaki - Web page: https://patentgrep.com/patent/US10312267B2 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/1334: based on polymer dispersed liquid crystals, e.g. microencapsulated liquid crystals - G02F 1/134309: {characterised by their geometrical arrangement} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G09G 3/2007: {Display of intermediate tones} - G09G 3/36: using liquid crystals - H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} - H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device} - H10D 30/674: {characterised by the active materials} - H10D 30/6756: {Amorphous oxide semiconductors} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/402: {Amorphous materials} - H10D 62/80: characterised by the materials - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - G02F 1/133302: {Rigid substrates, e.g. inorganic substrates} - G02F 1/13345: {Network or three-dimensional gels} - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0252: Improving the response speed - G09G 2320/0257: Reduction of after-image effects - G09G 2330/021: Power management, e.g. power saving - H10D 84/0128: {Manufacturing their channels} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract An object is to improve the drive capability of a semiconductor device. The semiconductor device includes a first transistor and a second transistor. A first terminal of the first transistor is electrically connected to a first wiring. A second terminal of the first transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to a third wiring. A first terminal of the second transistor is electrically connected to the third wiring. A second terminal of the second transistor is electrically connected to a gate of the first transistor. A channel region is formed using an oxide semiconductor layer in each of the first transistor and the second transistor. The off-state current of each of the first transistor and the second transistor per channel width of 1 μm is 1 aA or less. ## Claims ### Claim 1 A display device comprising: a pixel portion; and a circuit for driving the pixel portion, wherein the circuit comprises a first transistor and a second transistor, wherein one of a source and a drain of the first transistor is electrically connected to a wiring, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the wiring, wherein a gate of the second transistor is electrically connected to the wiring, wherein a signal is input to the wiring, wherein each of the first transistor and the second transistor comprise an oxide semiconductor layer comprising a channel region, and wherein the oxide semiconductor layer comprises In, Ga and Zn. ### Claim 2 (depends on 1) The display device according to claim 1, wherein the signal is a clock signal. ### Claim 3 (depends on 1) The display device according to claim 1, wherein the oxide semiconductor layer comprises a c-axis aligned crystal. ### Claim 4 A display device comprising: a pixel portion; and a circuit for driving the pixel portion, wherein the circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring, wherein a gate of the second transistor is electrically connected to the first wiring, wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring, wherein a signal is input to the first wiring, wherein a constant voltage is applied to the second wiring, wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor comprise an oxide semiconductor layer comprising a channel region, and wherein the oxide semiconductor layer comprises In, Ga and Zn. ### Claim 5 (depends on 4) The display device according to claim 4, wherein the signal is a clock signal. ### Claim 6 (depends on 4) The display device according to claim 4, wherein the oxide semiconductor layer comprises a c-axis aligned crystal. ### Claim 7 A display device comprising: a pixel portion; and a circuit for driving the pixel portion, wherein the circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein one of a source and a drain of the second transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the first wiring, wherein a gate of the second transistor is electrically connected to the first wiring, wherein one of a source and a drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the second wiring, wherein one of a source and a drain of the fifth transistor is electrically connected to the other of the source and the drain of the first transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to the second wiring, wherein a gate of the fifth transistor is electrically connected to a gate of the sixth transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the first transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to the second wiring, wherein a signal is input to the first wiring, wherein a constant voltage is applied to the second wiring, wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor comprise an oxide semiconductor layer comprising a channel region, and wherein the oxide semiconductor layer comprises In, Ga and Zn. ### Claim 8 (depends on 7) The display device according to claim 7, wherein the signal is a clock signal. ### Claim 9 (depends on 7) The display device according to claim 7, wherein the oxide semiconductor layer comprises a c-axis aligned crystal.