# US 10,312,261 B2 · Transistor with self-aligned source and drain contacts and method of making same

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- Number: US 10,312,261 B2
- Document ID: US10312261B2
- Status: Granted
- Kind: B2
- Application number: 15/890,910
- Filed: 2018-02-07
- Published: 2018-06-14
- Granted: 2019-06-04
- Earliest claimed: 2015-08-10
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics, Inc.
- Inventors: John Hongguang Zhang
- Web page: https://patentgrep.com/patent/US10312261B2

## CPC

- H10D 86/215: {comprising FinFETs}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/0212: {using self-aligned silicidation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A transistor includes an active region supported by a substrate and having a source region, a channel region and a drain region. A gate stack extends over the channel region and a first sidewall surrounds the gate stack. A raised source region and a raised drain region are provided over the source and drain regions, respectively, of the active region adjacent the first sidewall. A second sidewall peripherally surrounds each of the raised source region and raised drain region. The second sidewall extends above a top surface of the raised source region and raised drain region to define regions laterally delimited by the first and second sidewalls. A conductive material fills the regions to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

## Claims

### Claim 1

A method, comprising:
forming an intermediate transistor structure including:
a gate structure having a first vertical dielectric spacer on a first sidewall of the gate structure and having a second vertical dielectric spacer on a second sidewall of the gate structure,
a source region adjacent the gate structure such that at least part of the first vertical dielectric spacer is located between the source region and the gate structure; and
a drain region adjacent the gate structure such that at least part of the second vertical dielectric spacer is located between the source region and the gate structure;
wherein the top surface of the gate structure is at a level that is higher than and not coplanar with a top surface of the source region and a top surface of the drain region;
forming a sacrificial layer over the source region and the drain region so that a top surface of the sacrificial layer is substantially coplanar with the top surface of the gate structure;
forming a gate structure block mask over a portion of the gate structure, such that the gate structure block mask is not over at least a majority of the source region and the drain region;
forming a source/drain mask over the source region and the drain region adjacent the gate structure block mask;
while forming the source/drain mask, exposing a third sidewall and a fourth sidewall of the gate structure, wherein the third and fourth sidewalls are not parallel to nor aligned with the first and second sidewalls of the gate structure;
forming a third vertical dielectric spacer on any exposed sidewalls of the source region, on any exposed sidewalls of the drain region, on the third sidewall of the gate structure, and on the fourth sidewall of the gate structure;
selectively removing the source/drain mask;
selectively removing the sacrificial layer remaining on the source and drain regions;
forming source and drain contact structures on the source and drain regions at the locations where the remaining sacrificial layer was removed.

### Claim 2 (depends on 1)

The method of claim 1, wherein the sacrificial layer is made of a dielectric material.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the sacrificial layer comprises chemical vapor depositing of the sacrificial layer.

### Claim 4 (depends on 2)

The method of claim 2, wherein the sacrificial layer has a thickness between 400 nm and 600 nm.

### Claim 5 (depends on 2)

The method of claim 2, wherein forming the sacrificial layer comprises plasma enhanced chemical vapor depositing of the sacrificial layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate structure block mask is made of SiON.

### Claim 7 (depends on 6)

The method of claim 6, wherein forming the gate structure block mask comprises plasma enhanced chemical vapor depositing of the gate structure block mask.

### Claim 8 (depends on 6)

The method of claim 6, wherein the gate structure block mask has a thickness that is less than 80 nm.

### Claim 9 (depends on 1)

The method of claim 1, wherein the source/drain mask is made of an amorphous carbon-based material.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the source/drain mask comprises plasma enhanced chemical vapor depositing of the source/drain mask.

### Claim 11 (depends on 10)

The method of claim 10, wherein an initial thickness the source/drain mask is greater than a thickness of the gate structure block mask.

### Claim 12 (depends on 11)

The method of claim 11, forming the source/drain mask further comprises planarizing the source/drain mask to a level substantially coplanar with a top surface of the gate structure block mask.

### Claim 13 (depends on 1)

The method of claim 1, wherein forming the source and drain contact structures comprises locating the source and drain contact structures within a boundary formed by the first, second and third vertical dielectric spacers.

### Claim 14 (depends on 1)

The method of claim 1, further comprising siliciding a top of the source and drain regions.

### Claim 15

A method, comprising:
forming a gate structure that includes a first sidewall and a second sidewall;
forming a first vertical dielectric spacer on the first sidewall and a second vertical dielectric spacer on the second sidewall;
forming a source region adjacent the gate structure with at least part of the first vertical dielectric spacer located between the source region and the gate structure;
forming a drain region adjacent the gate structure with at least part of the second vertical dielectric spacer located between the source region and the gate structure;
providing a sacrificial layer over the source region and the drain region, the sacrificial layer having a top surface that is substantially coplanar with a top surface of the gate structure and the first and second vertical dielectric spacers;
forming a gate structure block mask that extends over the gate structure and the first and second vertical dielectric spacers;
forming a source/drain mask on the dummy layer over the source region and the drain region adjacent the gate structure block mask;
while forming the source/drain mask, exposing a third sidewall and a fourth sidewall of the gate structure, wherein the third and fourth sidewalls are not parallel to nor aligned with the first and second sidewalls of the gate structure;
forming a third vertical dielectric spacer on any exposed sidewalls of the source region, on any exposed sidewalls of the drain region, on any exposed sidewalls of the source/drain mask, on any exposed sidewalls of the gate structure block mask, on the third sidewall of the gate structure, and on the fourth sidewall of the gate structure;
selectively removing the source/drain mask and the sacrificial layer to form openings over the source and drain regions that are delimited by the first, second and third vertical dielectric spacers; and
filling said openings with a conductive material to form source and drain contact structures.

### Claim 16 (depends on 15)

The method of claim 15, further comprising siliciding a top of the source and drain regions in said openings.

### Claim 17

A method, comprising:
forming an intermediate transistor structure including:
an active region supported by a substrate and including a source region, a channel region and a drain region; and
a gate stack over the channel region;
forming a first sidewall spacer on sidewalls of the gate stack;
epitaxially growing a raised source region and a raised drain region over the source and drain regions, respectively, of the active region and adjacent the first sidewall spacer;
depositing a sacrificial layer over the raised source region and raised drain region to form a source stack and a drain stack, respectively;
forming a second sidewall spacer on further sidewalls of the gate stack and which peripherally surrounds the source stack and drain stack;
selectively removing the sacrificial layer to form openings above the raised source region and raised drain region that are each delimited by the first and second sidewall spacers; and
filling said openings with conductive material to form a source contact and a drain contact to the raised source region and raised drain region, respectively.

### Claim 18

A method, comprising:
forming an intermediate transistor structure including:
an active region supported by a substrate and including a source region, a channel region and a drain region; and
a gate stack over the channel region;
forming a first sidewall spacer on first sidewalls of the gate stack;
forming a raised source region and a raised drain region over the source and drain regions, respectively, of the active region and adjacent the first sidewall spacer;
depositing a sacrificial layer over the raised source region and raised drain region;
forming a first mask over the gate stack;
forming a second mask over the sacrificial layer and the raised source region and raised drain region;
etching using the first and second masks to define a source stack and drain stack covered by said second mask and expose second sidewalls of the gate stack;
forming a second sidewall spacer on the second sidewalls and which surrounds the source stack and drain stack;
removing the second mask;
etching using the first mask to remove the sacrificial layer and form openings above the raised source region and raised drain region which are delimited by the first and second sidewall spacers; and
filling said openings with conductive material to form a source contact and a drain contact to the raised source region and raised drain region, respectively.