# US 10,312,260 B2 · GaN transistors with polysilicon layers used for creating additional components

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- Number: US 10,312,260 B2
- Document ID: US10312260B2
- Status: Granted
- Kind: B2
- Application number: 15/655,508
- Filed: 2017-07-20
- Published: 2017-11-16
- Granted: 2019-06-04
- Earliest claimed: 2013-07-29
- Assignees: Efficient Power Conversion Corporation
- Applicants: Efficient Power Conversion Corporation
- Inventors: Jianjun Cao; Robert Beach; Alexander Lidow; Alana Nakata; Guangyuan Zhao; Yanping Ma; Robert Strittmatter; Michael A. de Rooij; Chunhua Zhou; Seshadri Kolluri; Fang-Chang Liu; Ming-Kun Chiang; Jiali Cao; Agus Jauhar
- Web page: https://patentgrep.com/patent/US10312260B2

## CPC

- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/40: Crystalline structures
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/517: {characterised by the conducting layers}
- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/82: of only field-effect components
- H10D 86/01: Manufacture or treatment
- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 62/343: {Gate regions of field-effect devices having PN junction gates}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

## Claims

### Claim 1

A method of manufacturing an integrated circuit, the method comprising:
depositing a channel layer over at least one buffer layer;
depositing a barrier layer over the channel layer, such that a two dimensional electron gas (2DEG) region is formed at an interface between the channel layer and the barrier layer;
forming an isolation region in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;
forming a gate structure for an enhancement mode device over the first portion of the 2DEG region;
depositing a first insulating layer over the gate structure;
forming a back gate over the second portion of the 2DEG region;
depositing a second insulating layer over the back gate;
depositing a polysilicon layer on the second insulating layer and etching the polysilicon layer, such that at least a portion of the etched polysilicon layer is disposed over the back gate;
doping the etched polysilicon layer to form at least one p-type region in the polysilicon layer;
depositing a third insulating layer on the etched polysilicon layer; and
forming at least one metal interconnect layer on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the step of forming the back gate over the second portion of the 2DEG region comprises depositing a gate metal on the first insulating layer and etching the gate metal, such that the etched gate metal is disposed over the second portion of the 2DEG region.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the step of etching the gate metal comprises etching the gate metal and the first insulating layer to form a pair of contact windows extending to the barrier layer on opposite sides of the gate structure.

### Claim 4 (depends on 3)

The method according to claim 3, further comprising forming a source metal and a drain metal in the pair of contact windows, respectively, wherein at least a portion of the source metal and a portion of the drain metal are each disposed over the gate metal.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the step of depositing the second insulating layer further comprises depositing the second insulating layer on the source metal and the drain metal.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the steps of forming the gate structure over the first portion of the 2DEG region and forming the back gate over the second portion of the 2DEG region comprises:
depositing a p-type GaN layer over the barrier layer;
depositing a gate metal on the p-type GaN layer;
forming a patterned photoresist on a first portion of the gate metal disposed over the first portion of the 2DEG region and on a second portion of the gate metal disposed over the second portion of the 2DEG region; and
etching the gate metal and the p-type GaN layer.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the step, of forming the isolation region comprises one of ion implantation in or etching of the barrier layer and the channel layer.

### Claim 8 (depends on 1)

The method according to claim 1, wherein the step of doping the polysilicon layer further comprises doping the polysilicon layer to form at least one n-type region in the polysilicon layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the step of doping the polysilicon layer further comprises forming either a second n-type region or a second p-type region, such that the doped polysilicon layer comprises either a PNP layer or an NPN layer as a source, a gate and a drain of an FET device.

### Claim 10

An integrated circuit comprising:
a channel layer disposed over at least one buffer layer;
a barrier layer disposed over the channel layer, with a two dimensional electron gas (2DEG) region formed at an interface between the channel layer and the barrier layer;
an isolation region disposed in the barrier layer and the channel layer to electrically isolate a first portion of the 2DEG region from a second portion of the 2DEG region;
a gate structure for an enhancement mode device disposed over the first portion of the 2DEG region;
a first insulating layer disposed over the gate structure;
a back gate disposed over the second portion of the 2DEG region;
a second insulating layer disposed over the back gate;
a polysilicon layer disposed on the second insulating layer and over the back gate, the polysilicon layer including at least one p-type region;
a third insulating layer disposed on the etched polysilicon layer; and
at least one metal interconnect layer disposed on the third insulating layer that is electrically coupled to the at least one p-type region of the polysilicon layer by at least one via formed in the third insulating layer.

### Claim 11 (depends on 10)

The integrated circuit according to claim 10, wherein the back gate over the second portion of the 2DEG region is disposed on the first insulating layer.

### Claim 12 (depends on 11)

The integrated circuit according to claim 11, further comprising a pair of contact windows extending through the gate metal and the first insulating layer to the barrier layer on opposite sides of the gate structure.

### Claim 13 (depends on 12)

The integrated circuit according to claim 12, further comprising a source metal and a drain metal disposed in the pair of contact windows, respectively, wherein at least a portion of the source metal and a portion of the drain metal are each disposed over the gate metal.

### Claim 14 (depends on 13)

The integrated circuit according to claim 13, wherein the second insulating layer is disposed on the source metal and the drain metal.

### Claim 15 (depends on 11)

The integrated circuit according to claim 11, wherein the gate structure and the back gate each comprise a p-type GaN layer disposed over the barrier layer and a gate metal disposed on the p-type GaN layer.

### Claim 16 (depends on 10)

The integrated circuit according to claim 10, wherein the polysilicon layer further comprises at least one n-type region.

### Claim 17 (depends on 16)

The integrated circuit according to claim 16, wherein the polysilicon layer further comprises either a second n-type region or a second p-type region, such that the doped polysilicon layer comprises either a PNP layer or an NPN layer as a source, a gate and a drain of an FET device.