# US 10,312,259 B2 · Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same

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- Number: US 10,312,259 B2
- Document ID: US10312259B2
- Status: Granted
- Kind: B2
- Application number: 15/220,608
- Filed: 2016-07-27
- Published: 2016-11-17
- Granted: 2019-06-04
- Earliest claimed: 2014-04-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bruce B. Doris; Lisa F. Edge; Pouya Hashemi; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10312259B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/6748: {having a multilayer structure or superlattice structure}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/01: Manufacture or treatment
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/425: {having different crystal properties in different TFTs or within an individual TFT}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3466: {Crystal orientation}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Multiple threshold voltage devices on hybrid oriented substrates, and methods of manufacturing same are disclosed. A method for manufacturing a semiconductor device comprises performing a single epitaxy step on a hybrid orientation substrate including a first region having a first crystallographic orientation and a second region having a second crystallographic orientation different from the first crystallographic orientation, wherein the single epitaxy step forms a first layer disposed on the first region and a second layer disposed on the second region, the first layer has the first crystallographic orientation and a first composition, and the second layer has the second crystal orientation and a second composition different from the first composition.

## Claims

### Claim 1

A semiconductor device, comprising:
a hybrid orientation substrate including a first silicon region having a first crystallographic orientation and a second silicon region having a second crystallographic orientation different from the first crystallographic orientation;
wherein the first silicon region and the second silicon region are formed on a top surface of a buried insulating layer formed on a semiconductor substrate, and a portion of the second silicon region is in contact with the semiconductor substrate through a contact hole in the buried insulating layer;
a first layer disposed on the first silicon region and having the first crystallographic orientation and a first composition;
a second layer disposed on the second silicon region and having the second crystallographic orientation and a second composition different from the first composition;
wherein the first and second compositions each comprises silicon germanium (SiGe);
a lower isolation region formed between the first and second silicon regions, wherein the lower isolation region is coplanar with the first and second silicon regions;
a plurality of upper isolation regions disposed on the first silicon region and on opposite lateral sides of the first layer;
wherein the first layer is disposed on part of a top surface of the first silicon region without covering all of the top surface of the first silicon region, and the second layer is disposed on part of a top surface of the second silicon region without covering all of the top surface of the second silicon region; and
a third layer disposed on the top surface of the first silicon region adjacent the first layer in a lateral direction, wherein the third layer has the first crystallographic orientation and a third composition different from the first and second compositions.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the first and second layers have different thicknesses from each other.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the first and second compositions each comprises different percentages of germanium from each other.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, further comprising a fourth layer disposed on the top surface of the second silicon region adjacent the second layer in a lateral direction, wherein the fourth layer has the second crystallographic orientation.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, further comprising a first upper isolation region of the plurality of upper isolation regions formed between the first and third layers and a second upper isolation region formed between the second and fourth layers.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein the first layer and the third layer are disposed on part of the first silicon region without covering all of the top surface of the first silicon region, and the second layer and the fourth layer are disposed on part of the second silicon region without covering all of the top surface of the second silicon region.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4, wherein the third and fourth layers have different thicknesses from each other.

### Claim 8

A semiconductor device, comprising:
a hybrid orientation substrate including a first silicon region having a first crystallographic orientation and a second silicon region having a second crystallographic orientation different from the first crystallographic orientation;
wherein the first silicon region and the second silicon region are formed on a top surface of a buried insulating layer formed on a semiconductor substrate, and a portion of the second silicon region is in contact with the semiconductor substrate through a contact hole in the buried insulating layer;
a first layer disposed on the first silicon region and having the first crystallographic orientation and a first composition;
a second layer disposed on the second silicon region and having the second crystallographic orientation and a second composition different from the first composition;
wherein the first and second compositions each comprises silicon germanium (SiGe);
a lower isolation region formed between the first and second silicon regions, wherein the lower isolation region is coplanar with the first and second silicon regions;
a third layer disposed on a top surface of the first silicon region adjacent the first layer in a lateral direction, wherein the third layer has the first crystallographic orientation and a third composition different from the first and second compositions;
a fourth layer disposed on a top surface of the second silicon region adjacent the second layer in a lateral direction, wherein the fourth layer has the second crystallographic orientation; and
a first upper isolation region formed between the first and third layers and a second upper isolation region formed between the second and fourth layers;
wherein the first layer is disposed on part of the top surface of the first silicon region without covering all of the top surface of the first silicon region, and the second layer is disposed on part of the top surface of the second silicon region without covering all of the top surface of the second silicon region;
wherein the first upper isolation region is coplanar with the first layer and not coplanar with the third layer; and
wherein the second upper isolation region is coplanar with the second layer and not coplanar with the fourth layer.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein the first and second layers have different thicknesses from each other.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8, wherein the first and second compositions each comprises different percentages of germanium from each other.

### Claim 11 (depends on 8)

The semiconductor device according to claim 8, wherein the third layer is disposed on part of the top surface of the first silicon region without covering all of the top surface of the first silicon region, and the fourth layer is disposed on part of the top surface of the second silicon region without covering all of the top surface of the second silicon region.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8, wherein the third and fourth layers have different thicknesses from each other.