# US 10,312,258 B2 · Semiconductor device with buried cavities and dielectric support structures

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- Number: US 10,312,258 B2
- Document ID: US10312258B2
- Status: Granted
- Kind: B2
- Application number: 15/209,206
- Filed: 2016-07-13
- Published: 2016-11-03
- Granted: 2019-06-04
- Earliest claimed: 2014-09-08
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Johannes Laven; Matteo Dainese; Hans-Joachim Schulze
- Web page: https://patentgrep.com/patent/US10312258B2

## CPC

- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 1/68: Capacitors having no potential barriers
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/278: {Pendeoepitaxy}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 14/6306: {of the semiconductor materials}
- H10P 50/283: {by chemical means}
- H10P 90/1912: {using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 95/906: {for altering the shape of semiconductors, e.g. smoothing the surface}
- H10W 10/0123: {using auxiliary pillars in the regions}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/427: {Power or ground buses}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10P 50/73: {using masks for insulating materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate with a first surface. The device further includes one or more semiconductor devices formed or the first surface in an active area. The device further includes a plurality of cavities in the semiconductor substrate beneath the first surface. The device further includes dielectric support structures between each of the cavities and spaced apart from the first surface. The dielectric support structures support a part of the semiconductor substrate between the active area and the cavities. The dielectric support structures include an oxide.

## Claims

### Claim 1

A semiconductor device, comprising;
a semiconductor substrate with a first surface;
one or more semiconductor devices formed on the first surface in an active area;
a plurality of enclosed cavities in the semiconductor substrate beneath the first surface; and
dielectric support structures between two adjacent ones of the cavities in the plurality and spaced apart from the first surface,
a region of semiconductor material extending to the first surface of the semiconductor substrate and covering the plurality of enclosed cavities and the dielectric support structures, the region of semiconductor material comprising the active area,
wherein the dielectric support structures comprise an oxide, and
wherein the dielectric support structures extend along outer sidewalls of the two adjacent ones of the cavities in the plurality,
wherein the plurality of enclosed cavities in the semiconductor substrate and the dielectric support structures collectively form a buried insulator layer disposed in the semiconductor substrate beneath the first surface, and wherein the buried insulator layer comprises an undulating upper side directly adjoining a lower side of the region of semiconductor material.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein each of the cavities in the plurality and the dielectric support structures form a buried insulator layer electrically insulating the active area from a subjacent region of the semiconductor substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising an access trench extending from the first surface to a first one of the cavities in the plurality, wherein the access trench and the first cavity are filled with an electrically conductive material.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the access trench and the first cavity enclose a device area of the semiconductor substrate such that the device area is laterally insulated from adjacent portions of the semiconductor substrate, wherein the device area comprises one or more semiconductor devices.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein one or more of the cavities in the plurality and the dielectric support structures form a buried insulator layer inside of the first cavity beneath the first surface such that a three-dimensional region of semiconductor material inside the access trench is completely electrically insulated from adjacent portions of the semiconductor substrate.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the access trench and the first cavity are configured as a charge storing capacitor that is electrically connected to one of the semiconductor devices.

### Claim 7

An SOI substrate, comprising;
a semiconductor substrate with a first surface and a second surface opposite the first surface;
an insulating layer disposed in the semiconductor substrate between the first and second surfaces; and
an active area of the semiconductor substrate comprising a semiconductor material disposed between the insulating layer and the first surface, and
wherein the insulating layer comprises:
an undulating upper side directly adjoining a lower side of the active area; and
a plurality of dielectric support structures spaced apart from one another at regular intervals, wherein each of the dielectric support structures in the plurality are vertical columns of oxide that extend in a direction perpendicular to the first and second surfaces, and wherein the each of dielectric support structures in the plurality support the active area of the semiconductor substrate.

### Claim 8 (depends on 7)

The SOI substrate of claim 7, wherein the insulating layer further comprises a plurality of electrically insulating regions disposed between adjacent spaced apart pairs of the dielectric support structures in the plurality.

### Claim 9 (depends on 8)

The SOI substrate of claim 8, wherein the plurality of electrically insulating regions comprises a plurality of unfilled cavities containing air.

### Claim 10 (depends on 7)

The SOI substrate of claim 7, wherein the undulating upper side of the insulating layer comprises a plurality of apexes that are disposed between the each of the dielectric support structures in the plurality and a plurality of nadirs directly adjoining two adjacent ones the dielectric support structures in the plurality, wherein the apexes are spaced closest to the first surface, and wherein the nadirs are furthest away from the first surface.

### Claim 11 (depends on 7)

The SOI substrate of claim 7, wherein the insulating layer completely insulates the active area of the semiconductor substrate from a subjacent region of the semiconductor substrate.

### Claim 12 (depends on 7)

The SOI substrate of claim 7, further comprising one or more semiconductor devices formed in the active area.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric support structures extend to a bottom side of the two adjacent ones of the cavities.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric support structures are vertical columns of oxide that extend in a direction perpendicular to the first surface.