# US 10,312,256 B1 · Method of manufacturing three-dimensional stacked semiconductor structure and structure manufactured by the same

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- Number: US 10,312,256 B1
- Document ID: US10312256B1
- Status: Granted
- Kind: B1
- Application number: 15/814,582
- Filed: 2017-11-16
- Published: 2019-05-16
- Granted: 2019-06-04
- Earliest claimed: 2017-11-16
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Guan-Ru Lee
- Web page: https://patentgrep.com/patent/US10312256B1

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/037: {comprising charge-trapping insulators}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 50/283: {by chemical means}
- H10W 20/0698: {Local interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A three-dimensional (3D) stacked semiconductor structure is provided. A substrate having an array area and a peripheral area is provided, and several patterned multi-layered stacks above the substrate are formed in the array area. The patterned multi-layered stacks are spaced apart from each other, and channel holes are formed between the patterned multi-layered stacks disposed adjacently. A charge trapping layer is formed on the patterned multi-layered stacks and deposited in the channel holes as liners. A polysilicon channel layer is deposited along the charge trapping layer, and conductive pads are formed on the polysilicon channel layer and respectively corresponding to the patterned multi-layered stacks. The polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), wherein the second thickness (t2) is larger than the first thickness (t1).

## Claims

### Claim 1

A three-dimensional (3D) stacked semiconductor structure, comprising:
a substrate, having an array area and a peripheral area;
patterned multi-layered stacks formed in the array area and above the substrate, and the patterned multi-layered stacks spaced apart from each other, and channel holes formed between the patterned multi-layered stacks disposed adjacently;
a charge trapping layer formed on the patterned multi-layered stacks and deposited in the channel holes as liners;
a polysilicon channel layer deposited along the charge trapping layer; and
conductive pads formed on the polysilicon channel layer and respectively formed above corresponding one of the patterned multi-layered stacks,
wherein one of the patterned multi-layered stacks comprises a plurality of insulating layers and a plurality of conductive layers arranged alternately,
wherein the plurality of conductive layers of one of the patterned multi-layered stacks has a first width (W1), one of the conductive pads has a second width (W2), and the second width (W2) is larger than the first width (W1),
wherein the polysilicon channel layer has a first thickness (t1), one of the conductive pads has a second thickness (t2), and the second thickness (t2) is larger than the first thickness (t1).

### Claim 2 (depends on 1)

The 3D stacked semiconductor structure according to claim 1, wherein a buried oxide layer is formed on the substrate, a bottom gate layer is formed on the buried oxide layer, and a bottom oxide layer is formed on the bottom gate layer, and one of the patterned multi-layered stacks is formed on the bottom oxide layer.

### Claim 3 (depends on 2)

The 3D stacked semiconductor structure according to claim 2, wherein the channel holes are vertical to the substrate and extended downwardly to stop on the buried oxide layer, wherein the charge trapping layer deposited in the channel holes is also formed on the buried oxide layer.

### Claim 4 (depends on 2)

The 3D stacked semiconductor structure according to claim 2, wherein the polysilicon channel layer and the buried oxide layer are separated by the charge trapping layer.

### Claim 5 (depends on 1)

The 3D stacked semiconductor structure according to claim 1, wherein a dielectric medium layer fills up rest spaces inside the channel holes, and conductive contacts are formed on and electrically connected to the conductive pads respectively.

### Claim 6 (depends on 1)

The 3D stacked semiconductor structure according to claim 1, wherein a ratio of the second thickness (t2) to the first thickness (t1) is in a range of 2 to 10.

### Claim 7 (depends on 1)

The 3D stacked semiconductor structure according to claim 1, wherein the second thickness (t2) is in a range of 200 Å to 600 Å.