# US 10,312,250 B1 · Semiconductor device and manufacturing method thereof

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- Number: US 10,312,250 B1
- Document ID: US10312250B1
- Status: Granted
- Kind: B1
- Application number: 15/878,278
- Filed: 2018-01-23
- Granted: 2019-06-04
- Earliest claimed: 2017-12-28
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Hsuan-Chun Tseng; Hsueh-Chun Hsiao; Tzu-Yun Chang; Chi-Cheng Huang; Ping-Chia Shih
- Web page: https://patentgrep.com/patent/US10312250B1

## CPC

- H10B 41/43: comprising only one type of peripheral transistor
- H10D 84/0158: {the components including FinFETs}
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
- H10B 43/30: characterised by the memory core region
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/212: {Through-implantation}
- H10P 30/22: using masks
- H10P 50/283: {by chemical means}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/834: {comprising FinFETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a memory region and a logic region, wherein the substrate in the memory region has a plurality of semiconductor fins;
a plurality of isolation structures disposed in the substrate to isolate the semiconductor fins, wherein the semiconductor fins are protruded beyond the isolation structures;
a charge storage layer covering the semiconductor fins;
a control gate disposed across the semiconductor fins and the isolation structures, such that the charge storage layer is disposed between the control gate and the semiconductor fins;
a select gate structure disposed on the substrate in the logic region and across the substrate and the isolation structures; and
a doped region located in the substrate between the select gate structure and the control gate, wherein the select gate structure and the control gate share the doped region.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the isolation structures is lower than a top surface of the semiconductor fins by a height difference.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the height difference is between 20 nm and 30 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the substrate in the memory region and a top surface of the substrate in the logic region are coplanar.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the charge storage layer comprises stacked layers of oxide-nitride-oxide.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a width of the semiconductor fins is between 5 nm and 20 nm.

### Claim 7

A manufacturing method of a semiconductor device, comprising:
providing a substrate comprising a memory region and a logic region;
forming a plurality of isolation structures in the substrate in the memory region and the logic region;
forming a pad oxide layer on the substrate in the memory region and the logic region;
removing the pad oxide layer in the memory region to recess the isolation structures, such that a plurality of portions of the substrate in the memory region is protruded beyond the isolation structures to form a plurality of semiconductor fins;
forming a charge storage layer to cover the semiconductor fins; and
forming a control gate disposed across the semiconductor fins and the isolation structures, such that the charge storage layer is disposed between the control gate and the semiconductor fins;
forming a select gate structure on the substrate in the logic region and across the substrate and the isolation structures; and
forming a doped region in the substrate between the select gate structure and the control gate after the select gate structure is formed, wherein the select gate structure and the control gate share the doped region.

### Claim 8 (depends on 7)

The manufacturing method of the semiconductor device of claim 7, wherein the step of removing the pad oxide layer in the memory region comprises:
forming a mask pattern to cover the pad oxide layer in the logic region;
performing a buffer oxide etching process for 5 seconds to 300 seconds to completely remove the pad oxide layer in the memory region and remove a portion of the isolation structures.

### Claim 9 (depends on 8)

The manufacturing method of the semiconductor device of claim 8, wherein an etch selectivity of the buffer oxide etching process on the isolation structures and the substrate is between 100 and 5.

### Claim 10 (depends on 7)

The manufacturing method of the semiconductor device of claim 7, wherein the step of removing the pad oxide layer in the memory region comprises:
forming a mask pattern to cover the pad oxide layer in the logic region;
performing an ion implantation process on the pad oxide layer in the memory region; and
performing a buffer oxide etching process for 5 seconds to 300 seconds to completely remove the pad oxide layer in the memory region and remove a portion of the isolation structures.

### Claim 11 (depends on 10)

The manufacturing method of the semiconductor device of claim 10, wherein the ion implantation process comprises implanting a dopant in the pad oxide layer in the memory region, and the dopant comprises carbon, phosphorus, arsenic, or a combination thereof.

### Claim 12 (depends on 7)

The manufacturing method of the semiconductor device of claim 7, wherein after the pad oxide layer in the memory region is removed to recess the isolation structures, a top surface of the isolation structures is lower than a top surface of the semiconductor fins by a height difference.

### Claim 13 (depends on 12)

The manufacturing method of the semiconductor device of claim 12, wherein the height difference is between 20 nm and 30 nm.

### Claim 14 (depends on 7)

The manufacturing method of the semiconductor device of claim 7, wherein a width of the semiconductor fins is between 5 nm and 20 nm.