# US 10,312,249 B2 · Method for forming a semiconductor device

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- Number: US 10,312,249 B2
- Document ID: US10312249B2
- Status: Granted
- Kind: B2
- Application number: 15/808,019
- Filed: 2017-11-09
- Published: 2019-05-09
- Granted: 2019-06-04
- Earliest claimed: 2017-11-09
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Wei-Chang Liu; Zhen Chen; Shen-De Wang; Chuan Sun; Wei Ta; Wang Xiang
- Web page: https://patentgrep.com/patent/US10312249B2

## CPC

- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10B 41/30: characterised by the memory core region
- H10B 43/40: characterised by the peripheral circuit region
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10P 30/22: using masks
- H10P 32/302: {Doping polycrystalline silicon or amorphous silicon layers}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.

## Claims

### Claim 1

A method for forming a semiconductor device, comprising:
providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprising a second polysilicon layer disposed within the second area on the substrate;
forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area;
patterning the organic material layer to form a patterned organic material layer, and the patterned organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer;
forming a patterned photo-resist layer on the patterned organic material layer; and
implanting the first polysilicon layer and the second polysilicon layer simultaneously.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the patterned organic material layer fully fills a first space between adjacent first semiconductor structures, wherein the first pre-determined region and second pre-determined region at the substrate are positioned correspondingly to the first space.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the patterned organic material layer fully fills a second space between the second semiconductor structure and one of the first semiconductor structures disposed adjacently.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the first space is narrower than the second space.

### Claim 5 (depends on 3)

The method according to claim 3,
wherein the patterned photo-resist layer further spans over the second space.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the first semiconductor structures are flash memory structures and the second semiconductor structure is a logic structure.

### Claim 7 (depends on 6)

The method according to claim 6, wherein said one of the flash memory structures further comprises a select gate and a spacer structure, wherein the first pre-determined region and the second pre-determined region are defined by the spacer structure disposed correspondingly to sidewalls of the memory gate and sidewalls of the select gate.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the spacer structure comprises:
first spacers, at least one of the first spaces disposed between the memory gate and the select gate, and two of the first spaces respectively disposed at the sidewalls of the memory gate and the sidewalls of the select gate; and
second spacers, disposed at outer sidewalls of the first spacers.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the organic material layer fully covers the first semiconductor structures within the first area and the second polysilicon layer within the second area.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the patterned organic material layer fully fills a space between the second polysilicon layer and at least one of the first semiconductor structures disposed adjacently.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the organic material layer comprises at least one of an advance patterning film, an organic dielectric layer, a silicon-containing organic layer and a photo-resist layer.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the patterned photo-resist layer shields a first part of the second polysilicon layer and un-shields a second part of the second polysilicon layer, so that the first polysilicon layer and the second part of the second polysilicon layer are implanted simultaneously.

### Claim 13 (depends on 1)

The method according to claim 1, further comprising:
removing the patterned photo-resist layer and the patterned organic material layer after simultaneously implanting the first polysilicon layer and the second polysilicon layer.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the patterned photo-resist layer formed on the patterned organic material layer further spans over a space between the second polysilicon layer and at least one of the first semiconductor structures disposed adjacently.

### Claim 15 (depends on 1)

The method according to claim 1, wherein the first polysilicon layers and the second polysilicon layer are formed of non-implanted polysilicon before forming the organic material layer.

### Claim 16 (depends on 1)

The method according to claim 1, wherein the first pre-determined region and the second pre-determined region are a source doping region and a drain doping region of the one of the flash memory structures, respectively.