# US 10,312,247 B1 · Two transistor FinFET-based split gate non-volatile floating gate flash memory and method of fabrication

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,247 B1
- Document ID: US10312247B1
- Status: Granted
- Kind: B1
- Application number: 15/933,124
- Filed: 2018-03-22
- Granted: 2019-06-04
- Earliest claimed: 2018-03-22
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Serguei Jourba; Catherine Decobert; Feng Zhou; Jinho Kim; Xian Liu; Nhan Do
- Web page: https://patentgrep.com/patent/US10312247B1

## CPC

- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 84/834: {comprising FinFETs}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A non-volatile memory cell formed on a semiconductor substrate having an upper surface with an upwardly extending fin with opposing first and second side surfaces. First and second electrodes are in electrical contact with first and second portions of the fin. A channel region of the fin includes portions of the first and second side surfaces that extend between the first and second portions of the fin. A floating gate extends along the first side surface of a first portion of the channel region, where no portion of the floating gate extends along the second side surface. A word line gate extends along the first and second side surfaces of a second portion of the channel region. A control gate is disposed over the floating gate. An erase gate has a first portion disposed laterally adjacent to the floating gate and a second portion disposed vertically over the floating gate.

## Claims

### Claim 1

A non-volatile memory cell comprising:
a semiconductor substrate having an upper surface with an upwardly extending fin that includes first and second side surfaces that oppose each other and an upwardly extending second fin that includes third and fourth side surfaces that oppose each other;
a first electrode in electrical contact with a first portion of the fin;
a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin;
a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein no portion of the floating gate extends along the second side surface, wherein at least a portion of the floating gate is disposed between the fin and the second fin and extends along and is insulated from the third side surface, and wherein no portion of the floating gate extends along the fourth side surface;
a word line gate that extends along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces;
a control gate disposed over and insulated from the floating gate;
an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically over and insulated from the floating gate.

### Claim 2 (depends on 1)

The non-volatile memory cell of claim 1, wherein no conductive gate is disposed along and insulated from a portion of the second side surface that is opposite to a portion of the first side surface along which the floating gate extends.

### Claim 3 (depends on 1)

The non-volatile memory cell of claim 1, wherein the word line gate includes a metal material, and wherein the word line gate is insulated from the first and second side surfaces by a high K insulation material.

### Claim 4 (depends on 1)

The non-volatile memory cell of claim 1, wherein the control gate and the erase gate each are disposed vertically over the fin.

### Claim 5 (depends on 1)

The non-volatile memory cell of claim 1, wherein the first and second portions of the fin each have a width that is greater than a width of the channel region of the fin.

### Claim 6 (depends on 1)

The non-volatile memory cell of claim 1, wherein the first and second portions of the fin each have a height that is greater than a height of the channel region of the fin.

### Claim 7 (depends on 1)

The non-volatile memory cell of claim 1, wherein the first electrode extends along the first and second side surfaces of the first portion of the fin, and wherein the second electrode extends along the first and second side surfaces of the second portion of the fin.

### Claim 8 (depends on 1)

The non-volatile memory cell of claim 1, wherein the floating gate has a rectangular vertical cross section.

### Claim 9 (depends on 1)

The non-volatile memory cell of claim 1, wherein the floating gate has a U-shape vertical cross section.

### Claim 10 (depends on 3)

The non-volatile memory cell of claim 3, wherein the floating gate, the control gate and the erase gate each include polysilicon material.

### Claim 11 (depends on 10)

The non-volatile memory cell of claim 10, wherein the first and second electrodes each include a metal material.

### Claim 12 (depends on 9)

The non-volatile memory cell of claim 9, wherein the control gate includes a lower portion that extends into the U-shape vertical cross section of the floating gate.

### Claim 13

A method of forming a non-volatile memory cell comprising:
forming trenches into an upper surface of a semiconductor substrate so that the upper surface includes an upwardly extending fin that includes first and second side surfaces that oppose each other and an upwardly extending second fin that includes third and fourth side surfaces that oppose each other;
forming a first electrode in electrical contact with a first portion of the fin;
forming a second electrode in electrical contact with a second portion of the fin, wherein the first and second portions of the fin are spaced apart from each other such that a channel region of the fin includes portions of the first and second side surfaces and extends between the first and second portions of the fin;
forming a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first side surface, wherein no portion of the floating gate extends along the second side surface, wherein at least a portion of the floating gate is disposed between the fin and the second fin and extends along and is insulated from the third side surface, and wherein no portion of the floating gate extends along the fourth side surface;
forming a word line gate that extends along a second portion of the channel region, wherein the word line gate extends along and is insulated from the first and second side surfaces;
forming a control gate disposed over and insulated from the floating gate;
forming an erase gate having a first portion disposed laterally adjacent to and insulated from the floating gate and a second portion disposed vertically over and insulated from the floating gate.

### Claim 14 (depends on 13)

The method of claim 13, wherein no conductive gate is disposed along and insulated from a portion of the second side surface that is opposite to a portion of the first side surface along which the floating gate extends.

### Claim 15 (depends on 13)

The method of claim 13, wherein the word line gate includes a metal material, and wherein the word line gate is insulated from the first and second side surfaces by a high K insulation material.

### Claim 16 (depends on 13)

The method of claim 13, wherein the floating gate, the control gate and the erase gate each include polysilicon material.

### Claim 17 (depends on 13)

The method of claim 13, wherein the control gate and the erase gate are each disposed vertically over the fin.

### Claim 18 (depends on 13)

The method of claim 13, wherein the first and second portions of the fin each have a width and a height that is greater than a width and a height respectively of the channel region of the fin.

### Claim 19 (depends on 13)

The method of claim 13, wherein the first electrode extends along the first and second side surfaces of the first portion of the fin, and wherein the second electrode extends along the first and second side surfaces of the second portion of the fin.

### Claim 20 (depends on 13)

The method of claim 13, wherein the floating gate has a rectangular vertical cross section.

### Claim 21 (depends on 13)

The method of claim 13, wherein the floating gate has a U-shape vertical cross section.

### Claim 22 (depends on 16)

The method of claim 16, wherein the first and second electrodes each include a metal material.

### Claim 23 (depends on 21)

The method of claim 21, wherein the control gate includes a lower portion that extends into the U-shape vertical cross section of the floating gate.