# US 10,312,245 B2 · Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared pFET and nFET trench

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- Number: US 10,312,245 B2
- Document ID: US10312245B2
- Status: Granted
- Kind: B2
- Application number: 16/117,811
- Filed: 2018-08-30
- Published: 2019-01-17
- Granted: 2019-06-04
- Earliest claimed: 2017-04-27
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Zuoguang Liu; Gen Tsutsui; Heng Wu; Peng Xu
- Web page: https://patentgrep.com/patent/US10312245B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/834: further characterised by the dopants
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3816: {Pulsed laser beam}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low contact resistance. The method includes forming a first semiconductor fin opposite a surface of a substrate and forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin. A doped region is formed over portions of each of the first and second semiconductor fins and a dielectric layer is formed over the doped regions. A shared trench is formed in the dielectric layer exposing portions of the doped regions. The exposed doped regions are then amorphized and recrystallized.

## Claims

### Claim 1

A semiconductor device comprising:
a first semiconductor fin formed opposite a surface of a substrate;
a second semiconductor fin formed opposite the surface of the substrate and adjacent to the first semiconductor fin;
a first doped region formed over portions of the first semiconductor fin;
a second doped region formed over portions of the second semiconductor fin; and
a shared conductive contact comprising a contact resistivity of less than about 2.5×10−9 Ω·cm−2 formed over the first and second doped regions.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first and second doped regions each comprise a crystalline structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first and second doped regions each comprise a polycrystalline structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first and second doped regions each comprises a Ge or Si dopant concentration of at least 1×1021 cm−3.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first doped region comprises p type dopants.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the p-type dopants are selected from the group consisting of B, BF2, Al, and Ga.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the second doped region comprises n type dopants.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the n-type dopants are selected from the group consisting of As, P, and Sb.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor fin and the second semiconductor fin are formed in a shared trench in a dielectric layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the first doped region comprises a first epitaxy region formed over the first semiconductor fin, wherein the first epitaxy region is doped with p-type dopants.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the second doped region comprises a second epitaxy region formed over the second semiconductor fin, wherein the second epitaxy region is doped with n-type dopants.

### Claim 12

A semiconductor device comprising:
a first semiconductor fin formed opposite a surface of a substrate;
a second semiconductor fin formed opposite the surface of the substrate and adjacent to the first semiconductor fin;
a first doped region comprising n type dopants formed over portions of the first semiconductor fin;
a second doped region comprising p type dopants formed over portions of the second semiconductor fin; and
a shared conductive contact comprising a contact resistivity of less than about 2.5×10−9 Ω·cm−2 formed over the first and second doped regions.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the first and second doped regions each comprise a crystalline structure.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the first and second doped regions each comprise a polycrystalline structure.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein the first and second doped regions each comprises a Ge or Si dopant concentration of at least 1×1021 cm−3.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the p-type dopants are selected from the group consisting of B, BF2, Al, and Ga.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, wherein the n-type dopants are selected from the group consisting of As, P, and Sb.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, wherein the first semiconductor fin and the second semiconductor fin are formed in a shared trench in a dielectric layer.

### Claim 19 (depends on 12)

The semiconductor device of claim 12, wherein the first doped region comprises a first epitaxy region formed over the first semiconductor fin, wherein the first epitaxy region is doped with n-type dopants.

### Claim 20 (depends on 12)

The semiconductor device of claim 12, wherein the second doped region comprises a second epitaxy region formed over the second semiconductor fin, wherein the second epitaxy region is doped with p-type dopants.