# US 10,312,244 B2 · Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage

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- Number: US 10,312,244 B2
- Document ID: US10312244B2
- Status: Granted
- Kind: B2
- Application number: 15/708,913
- Filed: 2017-09-19
- Published: 2019-03-21
- Granted: 2019-06-04
- Earliest claimed: 2017-09-19
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Xia Li; Seung Hyuk Kang; Bin Yang; Gengming Tao
- Web page: https://patentgrep.com/patent/US10312244B2

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/419: Read-write [R-W] circuits
- H10B 10/00: Static random access memory [SRAM] devices
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/177: {Base regions of bipolar transistors, e.g. BJTs or IGBTs}
- H10D 62/364: {of IGFETs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/8325: {Silicon carbide}
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 64/281: {Base electrodes for bipolar transistors}
- H10P 50/642: {Chemical etching}
- H10P 76/204: {of organic photoresist masks}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10B 10/10: SRAM devices comprising bipolar components
- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

## Claims

### Claim 1

A bi-stable static random access memory (SRAM) bit cell, comprising:
a substrate;
a well region formed in the substrate;
a source region formed adjacent to the well region, wherein a first bipolar junction transistor (BJT) is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the source region;
a drain region formed adjacent to the well region a distance from the source region, wherein a second BJT is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the drain region;
a gate region formed over the well region between the source region and the drain region;
a base tap region formed adjacent to the well region;
a collector tap region formed adjacent to the substrate;
a first shallow trench isolation (STI) region formed in the substrate adjacent to a first side of the well region and the source region, wherein a bottom surface of the first STI region is lower in the substrate than a bottom surface of the well region;
a second STI region formed in the substrate between the base tap region and the collector tap region and adjacent to a second side of the well region and the drain region, wherein a bottom surface of the second STI region is lower in the substrate than the bottom surface of the well region; and
a third STI region formed in the substrate between the drain region and the base tap region, wherein a bottom surface of the third STI region is higher in the well region than the bottom surface of the well region.

### Claim 2 (depends on 1)

The bi-stable SRAM bit cell of claim 1, wherein:
the source region is electrically coupled to a source line;
the drain region is electrically coupled to a bit line;
the gate region is electrically coupled to a word line;
the base tap region is electrically coupled to a base tap line; and
the collector tap region is electrically coupled to a collector tap line.

### Claim 3 (depends on 1)

The bi-stable SRAM bit cell of claim 1, wherein:
the substrate comprises a P-type material;
the well region is doped with an N-type material;
the source region is formed from the P-type material;
the drain region is formed from the P-type material;
the base tap region is formed from the N-type material; and
the collector tap region is formed from the P-type material.

### Claim 4 (depends on 3)

The bi-stable SRAM bit cell of claim 3, wherein:
the source region is formed from a material selected from the group consisting of: silicon-germanium (SiGe) and silicon (Si);
the drain region is formed from a material selected from the group consisting of: silicon-germanium (SiGe) and silicon (Si);
the base tap region is formed from a material selected from the group consisting of:
silicon-carbide (SiC) and silicon (Si); and
the collector tap region is formed from a material selected from the group consisting of:
silicon-germanium (SiGe) and silicon (Si).

### Claim 5 (depends on 3)

The bi-stable SRAM bit cell of claim 3, wherein the well region comprises a Fin comprising a top surface higher than a top surface of the first STI region, a top surface of the second STI region, and a top surface of the third STI region.

### Claim 6 (depends on 1)

The bi-stable SRAM bit cell of claim 1, further comprising a second well region disposed between the well region and the substrate, wherein:
the substrate comprises a P-type material;
the well region is doped with the P-type material;
the second well region is doped with an N-type material;
the source region is formed from the N-type material;
the drain region is formed from the N-type material;
the base tap region is formed from the P-type material; and
the collector tap region is formed from the P-type material.

### Claim 7 (depends on 5)

The bi-stable SRAM bit cell of claim 5, wherein:
the source region is formed from a material selected from the group consisting of: silicon-carbide (SiC) and silicon (Si);
the drain region is formed from a material selected from the group consisting of: silicon-carbide (SiC) and silicon (Si);
the base tap region is formed from a material selected from the group consisting of:
silicon-germanium (SiGe) and silicon (Si); and
the collector tap region is formed from a material selected from the group consisting of:
silicon-carbide (SiC) and silicon (Si).

### Claim 8 (depends on 6)

The bi-stable SRAM bit cell of claim 6, wherein the well region comprises a Fin comprising a top surface higher than a top surface of the first STI region, a top surface of the second STI region, and a top surface of the third STI region.

### Claim 9 (depends on 1)

The bi-stable SRAM bit cell of claim 1, wherein the gate region comprises:
a high-k dielectric oxide layer disposed over the well region; and
a metal layer disposed over the high-k dielectric oxide layer.

### Claim 10 (depends on 1)

The bi-stable SRAM bit cell of claim 1 integrated into an integrated circuit (IC).

### Claim 11 (depends on 1)

The bi-stable SRAM bit cell of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

### Claim 12

A static random access memory (SRAM) data array, comprising a plurality of bi-stable SRAM bit cells organized into a plurality of SRAM bit cell rows and a plurality of SRAM bit cell columns, wherein each bi-stable SRAM bit cell of the plurality of bi-stable SRAM bit cells corresponds to an SRAM bit cell row and an SRAM bit cell column, and comprises:
a substrate;
a well region formed in the substrate;
a source region formed adjacent to the well region, wherein a first bipolar junction transistor (BJT) is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the source region;
a drain region formed adjacent to the well region a distance from the source region, wherein a second BJT is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the drain region;
a gate region formed over the well region between the source region and the drain region;
a base tap region formed adjacent to the well region;
a collector tap region formed adjacent to the substrate;
a first shallow trench isolation (STI) region formed in the substrate adjacent to a first side of the well region and the source region, wherein a bottom surface of the first STI region is lower in the substrate than a bottom surface of the well region;
a second STI region formed in the substrate between the base tap region and the collector tap region and adjacent to a second side of the well region and the drain region, wherein a bottom surface of the second STI region is lower in the substrate than the bottom surface of the well region; and
a third STI region formed in the substrate between the drain region and the base tap region, wherein a bottom surface of the third STI region is higher in the well region than the bottom surface of the well region.

### Claim 13 (depends on 12)

The SRAM data array of claim 12, wherein:
the source region of each bi-stable SRAM bit cell is electrically coupled to a source line;
the drain region of each bi-stable SRAM bit cell is electrically coupled to a bit line;
the gate region of each bi-stable SRAM bit cell is electrically coupled to a word line; and
the collector tap region of each bi-stable SRAM bit cell is electrically coupled to a collector tap line.

### Claim 14 (depends on 12)

The SRAM data array of claim 12, wherein:
the substrate of each bi-stable SRAM bit cell comprises a P-type material;
the well region of each bi-stable SRAM bit cell is doped with an N-type material;
the source region of each bi-stable SRAM bit cell is formed from the P-type material;
the drain region of each bi-stable SRAM bit cell is formed from the P-type material;
the base tap region of each bi-stable SRAM bit cell is formed from the N-type material; and
the collector tap region of each bi-stable SRAM bit cell is formed from the P-type material.

### Claim 15 (depends on 14)

The SRAM data array of claim 14, wherein the well region of each bi-stable SRAM bit cell comprises a Fin comprising a top surface higher than a top surface of the first STI region, a top surface of the second STI region, and a top surface of the third STI region.

### Claim 16 (depends on 12)

The SRAM data array of claim 12, wherein each bi-stable SRAM bit cell further comprises a second well region disposed between the well region and the substrate, wherein:
the substrate comprises a P-type material;
the well region is doped with the P-type material;
the second well region is doped with an N-type material;
the source region is formed from the N-type material;
the drain region is formed from the N-type material;
the base tap region is formed from the P-type material; and
the collector tap region is formed from the P-type material.

### Claim 17 (depends on 16)

The SRAM data array of claim 16, wherein the well region of each bi-stable SRAM bit cell comprises a Fin comprising a top surface higher than a top surface of the first STI region, a top surface of the second STI region, and a top surface of the third STI region.

### Claim 18 (depends on 12)

The SRAM data array of claim 12, wherein the gate region of each bi-stable SRAM bit cell comprises:
a high-k dielectric oxide layer disposed over the well region; and
a metal layer disposed over the high-k dielectric oxide layer.

### Claim 19

A method for manufacturing a bi-stable static random access memory (SRAM) bit cell, comprising:
forming a first shallow trench isolation (STI) region, a second STI region, and a third STI region, wherein a bottom surface of the first STI region and a bottom surface of the second STI region is lower in a substrate than a bottom surface of the third STI region;
doping the substrate to form a well region such that a bottom surface of the well region is higher in the substrate than the bottom surfaces of the first STI region and the second STI region, and lower in the substrate than the bottom surface of the third STI region;
forming a gate region over the well region between the first STI region and the third STI region;
forming a source region adjacent to the well region between the first STI region and the gate region, wherein a first bipolar junction transistor (BJT) is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the source region;
forming a drain region adjacent to the well region between the third STI region and the gate region, wherein a second BJT is formed that comprises a base corresponding to the well region, a collector corresponding to the substrate, and an emitter corresponding to the drain region;
forming a base tap region adjacent to the well region between the second STI region and the third STI region; and
forming a collector tap region adjacent to the substrate adjacent to the second STI region.

### Claim 20 (depends on 19)

The method of claim 19, wherein forming the first STI region, the second STI region, and the third STI region comprises:
growing a pad oxide on the substrate;
depositing a hard mask layer over the pad oxide;
depositing a photoresist layer over the hard mask layer having a pattern corresponding to the first STI region, the second STI region, and the third STI region;
etching the hard mask layer and the pad oxide according to the pattern of the photoresist layer;
removing the photoresist layer;
etching the substrate to form the first STI region, the second STI region, and the third STI region such that the bottom surface of the first STI region and the bottom surface of the second STI region is lower in the substrate than the bottom surface of the third STI region;
filling the first STI region, the second STI region, and the third STI region with an STI oxide; and
removing excess STI oxide using chemical mechanical planarization (CMP);
removing the hard mask layer and the pad oxide.