# US 10,312,243 B2 · Semiconductor memory device and method of manufacturing the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,243 B2
- Document ID: US10312243B2
- Status: Granted
- Kind: B2
- Application number: 15/920,628
- Filed: 2018-03-14
- Published: 2019-01-24
- Granted: 2019-06-04
- Earliest claimed: 2017-07-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyun-jung Lee; Dongsoo Woo; Jin-Seong Lee; Namho Jeon; Jaeho Hong
- Web page: https://patentgrep.com/patent/US10312243B2

## CPC

- H10B 12/053: {the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10B 12/01: {Manufacture or treatment}
- H10B 12/50: {Peripheral circuit region structures}
- H10D 64/516: {the thicknesses being non-uniform}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/605: {Source, drain, or gate electrodes for FETs comprising highly resistive materials}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 32/30: Diffusion for doping of conductive or resistive layers
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

## Claims

### Claim 1

A semiconductor memory device comprising:
a separation member defining active regions of a substrate; and
gate lines intersecting the active regions and each buried in a trench formed in the substrate,
wherein each of the gate lines comprises: a lower electrode structure; and an upper electrode structure on the lower electrode structure,
wherein the upper electrode structure comprises:
a source layer substantially covering a sidewall of the trench and including a work-function adjustment element;
a conductive layer on the source layer; and
a work-function adjustment layer disposed between the source layer and the conductive layer,
wherein the work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein a work function of the lower electrode structure is higher than a work function of the upper electrode structure.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein the source layer and the conductive layer are spaced apart from each other by the work-function adjustment layer.

### Claim 4 (depends on 3)

The semiconductor memory device of claim 3, wherein the work-function adjustment layer conformally covers an inner sidewall of the source layer.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a gate insulating pattern on the sidewall of the trench, wherein the gate insulating pattern separates the gate line from the substrate, and
wherein a portion of the gate insulating pattern adjacent to the upper electrode structure laterally protrudes toward the conductive layer.

### Claim 6 (depends on 1)

The semiconductor memory device of claim 1, wherein the source layer extends between the lower electrode structure and the conductive layer to cover a top surface of the lower electrode structure.

### Claim 7 (depends on 6)

The semiconductor memory device of claim 6, wherein the source layer and the lower electrode structure have a gap provided therebetween, and
wherein the gap is substantially filled with oxygen or nitrogen.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1, wherein the work-function adjustment layer includes a metal or a metal nitride, and
wherein the work-function adjustment element includes lanthanum (La).

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
a diffusion layer disposed between the work-function adjustment layer and the conductive layer,
wherein the diffusion layer includes a same material as the work-function adjustment layer.

### Claim 10 (depends on 1)

The semiconductor memory device of claim 1, further comprising:
dopant injection regions disposed in the active regions, the dopant injection regions comprising: first dopant injections regions disposed in the active regions between the gate lines; and second dopant injection regions disposed in the active regions between the separation member and the gate lines;
bit lines provided on the substrate and connected to the first dopant injection regions; and
capacitors provided on the substrate and connected to the second dopant injection regions.

### Claim 11

A semiconductor memory device comprising:
a substrate comprising a separation member defining active regions arranged in a first direction;
gate lines each buried in a trench formed in an upper portion of the substrate, the gate lines intersecting the active regions in a second direction intersecting the first direction to divide the active regions into first dopant injection regions and second dopant injection regions; and
a bit line disposed on the gate lines and extending in a third direction intersecting both the first and second directions to intersect the gate lines,
wherein each of the gate lines comprises:
a first diffusion layer and a second diffusion layer formed along a bottom surface and a sidewall of the trench;
a work-function adjustment layer disposed between the first diffusion layer and the second diffusion layer; and
a conductive layer on the second diffusion layer,
wherein the first diffusion layer, the second diffusion layer and the work-function adjustment layer include a metal nitride, and
wherein the work-function adjustment layer is doped with a work-function adjustment element different from a metal element of the metal nitride.

### Claim 12 (depends on 11)

The semiconductor memory device of claim 11, wherein a work function of the work-function adjustment layer is lower than a work function of the first diffusion layer and a work function of the second diffusion layer.

### Claim 13 (depends on 11)

The semiconductor memory device of claim 11, further comprising:
a source layer disposed between at least one of the first diffusion layer and the work-function adjustment layer or between the second diffusion layer and the work-function adjustment layer.

### Claim 14 (depends on 13)

The semiconductor memory device of claim 13, wherein the source layer includes the work-function adjustment element of the work-function adjustment layer.

### Claim 15

A semiconductor memory device comprising:
a substrate comprising a plurality of active regions;
gate lines positioned in the active regions, wherein each of the gate lines is disposed in a trench formed in the substrate,
wherein each of the gate lines comprises: a lower electrode structure; and an upper electrode structure disposed on the lower electrode structure,
wherein the upper electrode structure comprises:
a source layer substantially covering a sidewall of the trench and including a work-function adjustment element;
a conductive layer on the source layer; and
a work-function adjustment layer disposed between the source layer and the conductive layer,
wherein the work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element; and
a gap formed between the lower electrode structure and the upper electrode structure.

### Claim 16 (depends on 15)

The semiconductor memory device of claim 15, wherein the gap is substantially filled with nitrogen or oxygen.