# US 10,312,242 B2 · Semiconductor memory device

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- Number: US 10,312,242 B2
- Document ID: US10312242B2
- Status: Granted
- Kind: B2
- Application number: 15/986,780
- Filed: 2018-05-22
- Published: 2019-01-10
- Granted: 2019-06-04
- Earliest claimed: 2017-07-07
- Assignees: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Tzu-Chieh Chen; Pin-Hong Chen; Chih-Chieh Tsai; Chia-Chen Wu; Yi-An Huang; Kai-Jiun Chang; Tsun-Min Cheng; Yi-Wei Chen
- Web page: https://patentgrep.com/patent/US10312242B2

## CPC

- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/09: {with simultaneous manufacture of the peripheral circuit region and memory cells}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/50: {Peripheral circuit region structures}
- H10W 74/147: {the encapsulations being multilayered}
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a substrate;
a plurality of gates disposed within the substrate;
a plurality of plugs disposed on the substrate, the plugs electrically connected to the substrate at two sides of the gate, respectively;
a capacitor structure disposed on the substrate, the capacitor structure comprising a plurality of capacitors, each of the capacitors electrically connected to the plugs respectively;
a semiconductor layer covering on the capacitor structure and directly in contact with the capacitor structure, where a portion of the semiconductor layer is filled between the capacitors;
a conductive cover layer covering on a top surface and insidewalls of the capacitor structure;
an adhesive layer covering on the conductive cover layer and the capacitor structure; and
an insulating layer covering the adhesive layer.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the adhesive layer comprises titanium, titanium nitride, tantalum, tantalum nitride, aluminum, tungsten nitride, or cobalt.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the adhesive layer comprises a multilayer structure.

### Claim 4 (depends on 3)

The semiconductor memory device according to claim 3, wherein the multilayer structure is selected from a group consisted of titanium, titanium nitride, tantalum, tantalum nitride, aluminum, tungsten nitride, and cobalt.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein another portion of the semiconductor layer covering on the sidewall of the capacitor structure has a greater thickness.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein another portion of the semiconductor layer covering on the sidewall of the capacitor structure has an uneven surface.

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein the conductive cover layer and the adhesive are conformally disposed on the semiconductor layer.

### Claim 8 (depends on 1)

The semiconductor memory device according to claim 1, wherein each of the capacitor comprises a lower electrode, a capacitor dielectric layer and an upper electrode, and each of the lower electrodes contacts the plugs.

### Claim 9 (depends on 1)

The semiconductor memory device according to claim 1, wherein the insulating layer comprise silicon oxide.