# US 10,312,240 B2 · Memory cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,240 B2 - Document ID: US10312240B2 - Status: Granted - Kind: B2 - Application number: 15/868,901 - Filed: 2018-01-11 - Published: 2018-05-17 - Granted: 2019-06-04 - Earliest claimed: 2016-08-31 - Assignees: STMicroelectronics S.r.l. - Applicants: Stmicroelectronics SA - Inventors: Hassan El Dirani; Yohann Solaro; Pascal Fonteneau - Web page: https://patentgrep.com/patent/US10312240B2 ## CPC - H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells} - G11C 11/409: Read-write [R-W] circuits - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 30/711: {having floating bodies} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion. ## Claims ### Claim 1 A microelectronic component comprising: A memory cell that includes: an insulating layer; a semiconductor layer overlying the insulating layer and including a doped source region, a doped drain region, and an intermediate region between the drain region and the source region; an insulated front gate electrode overlying the intermediate region; a first back gate electrode arranged under the insulating layer, opposite the drain region; and a second back gate electrode arranged under the insulating layer, opposite the source region; and a semiconductor substrate, wherein the insulating layer overlies the semiconductor substrate, the first back gate electrode including a first doped region of the semiconductor substrate and being of a first conductivity type, and the second back gate electrode including a second doped region of the semiconductor substrate and being of a second conductivity type. ### Claim 2 (depends on 1) The microelectronic component of claim 1, wherein the semiconductor substrate is a silicon substrate. ### Claim 3 (depends on 1) The microelectronic component of claim 1, wherein the semiconductor layer has a thickness between 5 and 30 nm, and wherein the insulating layer has a thickness between 5 and 30 nm. ### Claim 4 (depends on 1) The microelectronic component of claim 1, further comprising a controller configured to supply a first bias voltage to the first back gate electrode, a second bias voltage, different from the first bias voltage, to the second back gate electrode, a reference voltage to the source region, a first control signal to the drain region, and a second control signal to the front gate electrode. ### Claim 5 (depends on 4) The microelectronic component of claim 4, further comprising a silicon substrate, wherein the insulating layer overlies the silicon substrate, the first back gate electrode including a first doped silicon region of the silicon substrate and being of a first conductivity type, and the second back gate electrode including a second doped silicon region of the silicon substrate and being of a second conductivity type. ### Claim 6 (depends on 4) The microelectronic component of claim 4, wherein the semiconductor layer comprises silicon. ### Claim 7 A memory comprising: a memory cell that includes: a silicon substrate; an insulating layer that overlies the silicon substrate; a semiconductor layer overlying the insulating layer and including a doped source region, a doped drain region, and an intermediate region between the drain region and the source region; an insulated front gate electrode overlying the intermediate region; a first back gate electrode arranged under the insulating layer, opposite the drain region; and a second back gate electrode arranged under the insulating layer, opposite the source region; and a controller adapted to supply a first bias voltage to the first back gate electrode, a second bias voltage that is different than the first bias voltage to the second back gate electrode, a reference voltage to the source region, a first control signal to the drain region, and a second control signal to the front gate electrode. ### Claim 8 (depends on 7) The memory according to claim 7, wherein the controller is configured to: cause a first logic level to be programmed to the memory cell by setting the first control signal from the reference voltage to a first voltage level for a first time interval, and setting the second control signal from a second voltage level to the reference voltage for a second time interval included within the first time interval; cause a second logic level to be programmed to the memory cell by setting the second control signal from the second voltage level to the reference voltage for a third time interval; and read a logic value stored in the memory cell by setting the first control signal from the reference voltage to the first voltage level for a fourth time interval, the reference voltage being zero, the first voltage level and the second voltage level being greater in absolute value than the reference voltage. ### Claim 9 (depends on 7) The memory according to claim 7, wherein the controller is adapted to cause a first logic level to be programmed to the memory cell by setting the first control signal from the reference voltage to a first voltage level for a first time interval, and setting the second control signal from a second voltage level to the reference voltage for a second time interval included within the first time interval. ### Claim 10 (depends on 7) The memory according to claim 7, wherein the controller is adapted to cause a second logic level to be programmed to the memory cell by setting the second control signal from a second voltage level to the reference voltage for a third time interval. ### Claim 11 (depends on 7) The memory according to claim 7, wherein the controller is adapted to read a logic value stored in the memory cell by setting the first control signal from the reference voltage to a first voltage level for a fourth time interval. ### Claim 12 (depends on 7) The memory according to claim 7, wherein the semiconductor layer comprises silicon. ### Claim 13 (depends on 7) The memory according to claim 7, wherein the semiconductor layer has a thickness between 5 and 30 nm, and wherein the insulating layer has a thickness between 5 and 30 nm. ### Claim 14 A method, comprising: controlling a memory cell that comprises an insulating layer; a semiconductor layer that overlies the insulating layer and comprises a doped source region, a doped drain region, and an intermediate region between the drain region and the source region; an insulated front gate electrode overlying the drain region; a first back gate electrode arranged under the insulating layer, opposite the drain region; and a second back gate electrode arranged under the insulating layer, opposite the source, the controlling including: applying a first bias voltage to the first back gate electrode, a second bias voltage that is different than the first bias voltage to the second back gate electrode, and a reference voltage to the source region; and applying a first control signal to the drain region and a second control signal to the front gate electrode. ### Claim 15 (depends on 14) The method of claim 14, further comprising: writing a first logic value to the memory cell by setting the first control signal from the reference voltage to a first voltage level for a first time interval, and setting the second control signal from a second voltage level to the reference voltage for a second time interval included within the first time interval; writing a second logic value to the memory cell by setting the second control signal from the second voltage level to the reference voltage for a third time interval; and reading a logic value stored in the memory cell by setting the first control signal from the reference voltage to the first voltage level for a fourth time interval; wherein the reference voltage is zero and the first voltage level and the second voltage level are greater in absolute value than the reference voltage. ### Claim 16 (depends on 15) The method of claim 15, wherein writing the second logic value comprises maintaining the first control signal at the reference voltage and, wherein the reading comprises maintaining the second control signal at the second voltage level. ### Claim 17 (depends on 15) The method of claim 15, wherein the first voltage level and the second voltage level are positive, the first bias voltage is positive or zero, and the second bias voltage is negative or zero. ### Claim 18 (depends on 15) The method of claim 15, wherein the first voltage level and the second voltage level are negative, the first bias voltage is negative or zero, and the second bias voltage is positive or zero. ### Claim 19 (depends on 15) The method of claim 15, wherein the first voltage level and the second voltage level are smaller than 1 V in absolute value. ### Claim 20 (depends on 15) The method of claim 15, wherein, between two successive read or write operations, the first control signal is maintained at the reference voltage and the second control signal is maintained at the second voltage level. ### Claim 21 A microelectronic component comprising: A memory cell that includes: an insulating layer; a semiconductor layer overlying the insulating layer and including a doped source region, a doped drain region, and an intermediate region between the drain region and the source region; an insulated front gate electrode overlying the intermediate region; a first back gate electrode arranged under the insulating layer, opposite the drain region; a second back gate electrode arranged under the insulating layer, opposite the source region; a first bias terminal connected to the first back gate electrode; and a second bias terminal connected to the second back gate electrode. ### Claim 22 (depends on 21) The microelectronic component of claim 21, further comprising a semiconductor substrate, wherein the insulating layer overlies the semiconductor substrate, the first back gate electrode including a first doped region of the semiconductor substrate and being of a first conductivity type, and the second back gate electrode including a second doped region of the semiconductor substrate and being of a second conductivity type. ### Claim 23 (depends on 21) The microelectronic component of claim 21, further comprising a controller configured to supply a first bias voltage to the first back gate electrode, a second bias voltage, different from the first bias voltage, to the second back gate electrode, a reference voltage to the source region, a first control signal to the drain region, and a second control signal to the front gate electrode. ### Claim 24 (depends on 23) The microelectronic component of claim 23, further comprising a semiconductor substrate, wherein the insulating layer overlies the semiconductor substrate, the first back gate electrode including a first doped region of the silicon substrate and being of a first conductivity type, and the second back gate electrode including a second doped region of the semiconductor substrate and being of a second conductivity type. ### Claim 25 (depends on 21) The microelectronic component of claim 21, wherein the semiconductor layer comprises silicon.